ab3cffcfc2
The multiport Infiniband device support was introduced [1]. All active ports, belonging to the same Infiniband device use the single shared Infiniband context of that device and share the resources: - QPs are created within shared context - Verbs flows are also created with specifying port index - DV/DR resources - Protection Domain - Event Handlers This patchset adds support for Memory Regions sharing between ports, created on the base of multiport Infiniband device. The datapath of mlx5 uses the layered cache subsystem for allocating/releasing Memory Regions, only the lowest layer L3 is subject to share due to performance issues. [1] http://patches.dpdk.org/cover/51800/ Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
124 lines
3.8 KiB
C
124 lines
3.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2018 6WIND S.A.
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* Copyright 2018 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_MR_H_
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#define RTE_PMD_MLX5_MR_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <sys/queue.h>
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#include <infiniband/mlx5dv.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_eal_memconfig.h>
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#include <rte_ethdev.h>
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#include <rte_rwlock.h>
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#include <rte_bitmap.h>
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/* Memory Region object. */
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struct mlx5_mr {
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LIST_ENTRY(mlx5_mr) mr; /**< Pointer to the prev/next entry. */
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struct ibv_mr *ibv_mr; /* Verbs Memory Region. */
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const struct rte_memseg_list *msl;
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int ms_base_idx; /* Start index of msl->memseg_arr[]. */
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int ms_n; /* Number of memsegs in use. */
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uint32_t ms_bmp_n; /* Number of bits in memsegs bit-mask. */
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struct rte_bitmap *ms_bmp; /* Bit-mask of memsegs belonged to MR. */
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};
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/* Cache entry for Memory Region. */
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struct mlx5_mr_cache {
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uintptr_t start; /* Start address of MR. */
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uintptr_t end; /* End address of MR. */
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uint32_t lkey; /* rte_cpu_to_be_32(ibv_mr->lkey). */
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} __rte_packed;
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/* MR Cache table for Binary search. */
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struct mlx5_mr_btree {
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uint16_t len; /* Number of entries. */
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uint16_t size; /* Total number of entries. */
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int overflow; /* Mark failure of table expansion. */
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struct mlx5_mr_cache (*table)[];
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} __rte_packed;
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/* Per-queue MR control descriptor. */
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struct mlx5_mr_ctrl {
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uint32_t *dev_gen_ptr; /* Generation number of device to poll. */
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uint32_t cur_gen; /* Generation number saved to flush caches. */
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uint16_t mru; /* Index of last hit entry in top-half cache. */
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uint16_t head; /* Index of the oldest entry in top-half cache. */
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struct mlx5_mr_cache cache[MLX5_MR_CACHE_N]; /* Cache for top-half. */
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struct mlx5_mr_btree cache_bh; /* Cache for bottom-half. */
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} __rte_packed;
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struct mlx5_ibv_shared;
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extern struct mlx5_dev_list mlx5_mem_event_cb_list;
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extern rte_rwlock_t mlx5_mem_event_rwlock;
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/* First entry must be NULL for comparison. */
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#define mlx5_mr_btree_len(bt) ((bt)->len - 1)
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int mlx5_mr_btree_init(struct mlx5_mr_btree *bt, int n, int socket);
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void mlx5_mr_btree_free(struct mlx5_mr_btree *bt);
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uint32_t mlx5_mr_create_primary(struct rte_eth_dev *dev,
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struct mlx5_mr_cache *entry, uintptr_t addr);
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void mlx5_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
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size_t len, void *arg);
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int mlx5_mr_update_mp(struct rte_eth_dev *dev, struct mlx5_mr_ctrl *mr_ctrl,
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struct rte_mempool *mp);
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void mlx5_mr_release(struct mlx5_ibv_shared *sh);
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/* Debug purpose functions. */
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void mlx5_mr_btree_dump(struct mlx5_mr_btree *bt);
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void mlx5_mr_dump_dev(struct mlx5_ibv_shared *sh);
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/**
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* Look up LKey from given lookup table by linear search. Firstly look up the
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* last-hit entry. If miss, the entire array is searched. If found, update the
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* last-hit index and return LKey.
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*
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* @param lkp_tbl
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* Pointer to lookup table.
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* @param[in,out] cached_idx
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* Pointer to last-hit index.
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* @param n
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* Size of lookup table.
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* @param addr
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* Search key.
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*
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* @return
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* Searched LKey on success, UINT32_MAX on no match.
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*/
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static __rte_always_inline uint32_t
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mlx5_mr_lookup_cache(struct mlx5_mr_cache *lkp_tbl, uint16_t *cached_idx,
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uint16_t n, uintptr_t addr)
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{
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uint16_t idx;
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if (likely(addr >= lkp_tbl[*cached_idx].start &&
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addr < lkp_tbl[*cached_idx].end))
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return lkp_tbl[*cached_idx].lkey;
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for (idx = 0; idx < n && lkp_tbl[idx].start != 0; ++idx) {
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if (addr >= lkp_tbl[idx].start &&
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addr < lkp_tbl[idx].end) {
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/* Found. */
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*cached_idx = idx;
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return lkp_tbl[idx].lkey;
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}
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}
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return UINT32_MAX;
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}
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#endif /* RTE_PMD_MLX5_MR_H_ */
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