89fc6763b1
Avoid using PCI subsystem device id for SoC revision identification and just use PCI revision id to support C0 silicon. This patch also reduces SQB threshold to 70% to have sufficient buffer before we overflow SQ. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
143 lines
3.8 KiB
C
143 lines
3.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_DEV_H
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#define _OTX2_DEV_H
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#include <rte_bus_pci.h>
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#include "otx2_common.h"
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#include "otx2_irq.h"
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#include "otx2_mbox.h"
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#include "otx2_mempool.h"
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/* Common HWCAP flags. Use from LSB bits */
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#define OTX2_HWCAP_F_VF BIT_ULL(8) /* VF device */
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#define otx2_dev_is_vf(dev) (dev->hwcap & OTX2_HWCAP_F_VF)
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#define otx2_dev_is_pf(dev) (!(dev->hwcap & OTX2_HWCAP_F_VF))
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#define otx2_dev_is_lbk(dev) ((dev->hwcap & OTX2_HWCAP_F_VF) && \
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(dev->tx_chan_base < 0x700))
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#define otx2_dev_revid(dev) (dev->hwcap & 0xFF)
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#define otx2_dev_is_sdp(dev) (dev->sdp_link)
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#define otx2_dev_is_vf_or_sdp(dev) \
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(otx2_dev_is_vf(dev) || otx2_dev_is_sdp(dev))
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#define otx2_dev_is_A0(dev) \
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((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0))
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#define otx2_dev_is_Ax(dev) \
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((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0))
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#define otx2_dev_is_95xx_A0(dev) \
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((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1))
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#define otx2_dev_is_95xx_Ax(dev) \
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((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1))
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#define otx2_dev_is_96xx_A0(dev) \
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((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))
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#define otx2_dev_is_96xx_Ax(dev) \
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((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \
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(RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))
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struct otx2_dev;
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/* Link status callback */
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typedef void (*otx2_link_status_t)(struct otx2_dev *dev,
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struct cgx_link_user_info *link);
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/* PTP info callback */
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typedef int (*otx2_ptp_info_t)(struct otx2_dev *dev, bool ptp_en);
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struct otx2_dev_ops {
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otx2_link_status_t link_status_update;
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otx2_ptp_info_t ptp_info_update;
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};
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#define OTX2_DEV \
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int node __rte_cache_aligned; \
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uint16_t pf; \
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int16_t vf; \
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uint16_t pf_func; \
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uint8_t mbox_active; \
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bool drv_inited; \
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uint64_t active_vfs[MAX_VFPF_DWORD_BITS]; \
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uintptr_t bar2; \
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uintptr_t bar4; \
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struct otx2_mbox mbox_local; \
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struct otx2_mbox mbox_up; \
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struct otx2_mbox mbox_vfpf; \
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struct otx2_mbox mbox_vfpf_up; \
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otx2_intr_t intr; \
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int timer_set; /* ~0 : no alarm handling */ \
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uint64_t hwcap; \
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struct otx2_npa_lf npalf; \
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struct otx2_mbox *mbox; \
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uint16_t maxvf; \
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const struct otx2_dev_ops *ops
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struct otx2_dev {
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OTX2_DEV;
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};
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int otx2_dev_priv_init(struct rte_pci_device *pci_dev, void *otx2_dev);
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/* Common dev init and fini routines */
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static __rte_always_inline int
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otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
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{
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struct otx2_dev *dev = otx2_dev;
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uint8_t rev_id;
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int rc;
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rc = rte_pci_read_config(pci_dev, &rev_id,
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1, RVU_PCI_REVISION_ID);
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if (rc != 1) {
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otx2_err("Failed to read pci revision id, rc=%d", rc);
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return rc;
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}
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dev->hwcap = rev_id;
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return otx2_dev_priv_init(pci_dev, otx2_dev);
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}
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void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev);
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int otx2_dev_active_vfs(void *otx2_dev);
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#define RVU_PFVF_PF_SHIFT 10
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#define RVU_PFVF_PF_MASK 0x3F
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#define RVU_PFVF_FUNC_SHIFT 0
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#define RVU_PFVF_FUNC_MASK 0x3FF
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static inline int
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otx2_get_vf(uint16_t pf_func)
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{
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return (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1);
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}
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static inline int
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otx2_get_pf(uint16_t pf_func)
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{
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return (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
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}
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static inline int
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otx2_pfvf_func(int pf, int vf)
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{
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return (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);
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}
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static inline int
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otx2_is_afvf(uint16_t pf_func)
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{
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return !(pf_func & ~RVU_PFVF_FUNC_MASK);
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}
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#endif /* _OTX2_DEV_H */
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