8a4f835971
Various octeontx2 drivers use IO handling API, added octeontx2 specific IO handling routines in the common code. Since some of those implementations are based on arm64 instructions added the stub to compile the code on non arm64 ISA. The non arm64 ISA stub is possible due to the fact that it is an integrated controller i.e runs only on Marvell HW. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_IO_GENERIC_H_
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#define _OTX2_IO_GENERIC_H_
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#define otx2_load_pair(val0, val1, addr) \
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do { \
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val0 = rte_read64_relaxed((void *)(addr)); \
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val1 = rte_read64_relaxed((uint8_t *)(addr) + 8); \
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} while (0)
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#define otx2_store_pair(val0, val1, addr) \
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do { \
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rte_write64_relaxed(val0, (void *)(addr)); \
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rte_write64_relaxed(val1, (((uint8_t *)(addr)) + 8)); \
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} while (0)
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#define otx2_prefetch_store_keep(ptr) do {} while (0)
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static inline uint64_t
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otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)
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{
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RTE_SET_USED(ptr);
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RTE_SET_USED(incr);
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return 0;
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}
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static inline uint64_t
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otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)
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{
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RTE_SET_USED(ptr);
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RTE_SET_USED(incr);
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return 0;
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}
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static inline int64_t
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otx2_lmt_submit(uint64_t io_address)
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{
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RTE_SET_USED(io_address);
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return 0;
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}
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static __rte_always_inline void
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otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)
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{
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RTE_SET_USED(out);
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RTE_SET_USED(in);
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RTE_SET_USED(lmtext);
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}
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static __rte_always_inline void
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otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)
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{
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RTE_SET_USED(out);
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RTE_SET_USED(in);
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RTE_SET_USED(segdw);
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}
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#endif /* _OTX2_IO_GENERIC_H_ */
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