84ed1a5b4b
Add support to registering and un-registering SSO HWS and HWGRP IRQs. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _ROC_SSO_PRIV_H_
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#define _ROC_SSO_PRIV_H_
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struct sso_rsrc {
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uint16_t rsrc_id;
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uint64_t base;
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};
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struct sso {
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struct plt_pci_device *pci_dev;
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struct dev dev;
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/* Interrupt handler args. */
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struct sso_rsrc hws_rsrc[MAX_RVU_BLKLF_CNT];
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struct sso_rsrc hwgrp_rsrc[MAX_RVU_BLKLF_CNT];
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/* MSIX offsets */
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uint16_t hws_msix_offset[MAX_RVU_BLKLF_CNT];
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uint16_t hwgrp_msix_offset[MAX_RVU_BLKLF_CNT];
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/* SSO link mapping. */
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struct plt_bitmap **link_map;
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void *link_map_mem;
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} __plt_cache_aligned;
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enum sso_err_status {
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SSO_ERR_PARAM = -4096,
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};
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enum sso_lf_type {
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SSO_LF_TYPE_HWS,
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SSO_LF_TYPE_HWGRP,
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};
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static inline struct sso *
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roc_sso_to_sso_priv(struct roc_sso *roc_sso)
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{
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return (struct sso *)&roc_sso->reserved[0];
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}
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/* SSO IRQ */
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int sso_register_irqs_priv(struct roc_sso *roc_sso,
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struct plt_intr_handle *handle, uint16_t nb_hws,
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uint16_t nb_hwgrp);
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void sso_unregister_irqs_priv(struct roc_sso *roc_sso,
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struct plt_intr_handle *handle, uint16_t nb_hws,
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uint16_t nb_hwgrp);
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#endif /* _ROC_SSO_PRIV_H_ */
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