4cd1c5fd9e
Add meson based build infrastructure along with the OTX2 regexdev (REE) device functions. Add Marvell OCTEON TX2 regex guide. Signed-off-by: Guy Kaneti <guyk@marvell.com>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef _OTX2_REGEXDEV_H_
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#define _OTX2_REGEXDEV_H_
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#include <rte_common.h>
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#include <rte_regexdev.h>
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#include "otx2_dev.h"
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#define ree_func_trace otx2_ree_dbg
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/* Marvell OCTEON TX2 Regex PMD device name */
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#define REGEXDEV_NAME_OCTEONTX2_PMD regex_octeontx2
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#define OTX2_REE_MAX_LFS 36
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#define OTX2_REE_MAX_QUEUES_PER_VF 36
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#define OTX2_REE_MAX_MATCHES_PER_VF 254
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#define OTX2_REE_MAX_PAYLOAD_SIZE (1 << 14)
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#define OTX2_REE_NON_INC_PROG 0
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#define OTX2_REE_INC_PROG 1
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#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)
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/**
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* Device vf data
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*/
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struct otx2_ree_vf {
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struct otx2_dev otx2_dev;
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/**< Base class */
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uint16_t max_queues;
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/**< Max queues supported */
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uint8_t nb_queues;
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/**< Number of regex queues attached */
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uint16_t max_matches;
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/**< Max matches supported*/
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uint16_t lf_msixoff[OTX2_REE_MAX_LFS];
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/**< MSI-X offsets */
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uint8_t block_address;
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/**< REE Block Address */
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uint8_t err_intr_registered:1;
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/**< Are error interrupts registered? */
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};
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/**
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* Device private data
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*/
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struct otx2_ree_data {
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uint32_t regexdev_capa;
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uint64_t rule_flags;
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/**< Feature flags exposes HW/SW features for the given device */
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uint16_t max_rules_per_group;
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/**< Maximum rules supported per subset by this device */
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uint16_t max_groups;
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/**< Maximum subset supported by this device */
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void **queue_pairs;
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/**< Array of pointers to queue pairs. */
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uint16_t nb_queue_pairs;
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/**< Number of device queue pairs. */
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struct otx2_ree_vf vf;
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/**< vf data */
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struct rte_regexdev_rule *rules;
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/**< rules to be compiled */
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uint16_t nb_rules;
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/**< number of rules */
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} __rte_cache_aligned;
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struct otx2_ree_rid {
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uintptr_t rid;
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/** Request id of a ree operation */
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uint64_t user_id;
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/* Client data */
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/**< IOVA address of the pattern to be matched. */
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};
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struct otx2_ree_pending_queue {
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uint64_t pending_count;
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/** Pending requests count */
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struct otx2_ree_rid *rid_queue;
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/** Array of pending requests */
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uint16_t enq_tail;
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/** Tail of queue to be used for enqueue */
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uint16_t deq_head;
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/** Head of queue to be used for dequeue */
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};
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struct otx2_ree_qp {
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uint32_t id;
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/**< Queue pair id */
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uintptr_t base;
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/**< Base address where BAR is mapped */
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struct otx2_ree_pending_queue pend_q;
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/**< Pending queue */
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rte_iova_t iq_dma_addr;
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/**< Instruction queue address */
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uint32_t otx2_regexdev_jobid;
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/**< Job ID */
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uint32_t write_offset;
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/**< write offset */
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regexdev_stop_flush_t cb;
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/**< Callback function called during rte_regex_dev_stop()*/
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};
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#endif /* _OTX2_REGEXDEV_H_ */
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