5a93e173b8
The packets transmitting in mlx5 is performed by building
Tx descriptors (WQEs) and sending last ones to the NIC.
The descriptor can contain the special flags, telling the NIC
to generate Tx completion notification (CQEs). At the beginning
of tx_burst() routine PMD checks whether there are some Tx
completions and frees the transmitted packet buffers.
The flags to request completion generation must be set once
per specified amount of packets to provide uniform stream
of completions and freeing the Tx queue in uniform fashion.
The previous implementation sets the completion request
generation once per burst, if burst size if big enough it may
latency in CQE generation and freeing large amount of buffers
in tx_burst routine on multiple completions which also
affects the latency and even causes the Tx queue overflow
and Tx drops.
This patches enforces the completion request will be set
in the exact Tx descriptor if specified amount of packets
is already sent.
Fixes: 18a1c20044 ("net/mlx5: implement Tx burst template")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
142 lines
4.5 KiB
C
142 lines
4.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_DEFS_H_
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#define RTE_PMD_MLX5_DEFS_H_
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#include <rte_ethdev_driver.h>
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#include "mlx5_autoconf.h"
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/* Reported driver name. */
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#define MLX5_DRIVER_NAME "net_mlx5"
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/* Maximum number of simultaneous unicast MAC addresses. */
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#define MLX5_MAX_UC_MAC_ADDRESSES 128
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/* Maximum number of simultaneous Multicast MAC addresses. */
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#define MLX5_MAX_MC_MAC_ADDRESSES 128
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/* Maximum number of simultaneous MAC addresses. */
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#define MLX5_MAX_MAC_ADDRESSES \
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(MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
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/* Maximum number of simultaneous VLAN filters. */
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#define MLX5_MAX_VLAN_IDS 128
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/*
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* Request TX completion every time descriptors reach this threshold since
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* the previous request. Must be a power of two for performance reasons.
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*/
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#define MLX5_TX_COMP_THRESH 32u
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/*
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* Request TX completion every time the total number of WQEBBs used for inlining
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* packets exceeds the size of WQ divided by this divisor. Better to be power of
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* two for performance.
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*/
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#define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
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/*
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* Maximal amount of normal completion CQEs
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* processed in one call of tx_burst() routine.
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*/
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#define MLX5_TX_COMP_MAX_CQE 2u
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/* Size of per-queue MR cache array for linear search. */
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#define MLX5_MR_CACHE_N 8
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/* Size of MR cache table for binary search. */
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#define MLX5_MR_BTREE_CACHE_N 256
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/*
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* If defined, only use software counters. The PMD will never ask the hardware
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* for these, and many of them won't be available.
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*/
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#ifndef MLX5_PMD_SOFT_COUNTERS
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#define MLX5_PMD_SOFT_COUNTERS 1
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#endif
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/* Alarm timeout. */
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#define MLX5_ALARM_TIMEOUT_US 100000
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/* Maximum number of extended statistics counters. */
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#define MLX5_MAX_XSTATS 32
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/* Maximum Packet headers size (L2+L3+L4) for TSO. */
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#define MLX5_MAX_TSO_HEADER (128u + 34u)
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/* Inline data size required by NICs. */
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#define MLX5_INLINE_HSIZE_NONE 0
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#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_vlan_hdr))
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#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \
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sizeof(struct rte_ipv6_hdr))
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#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \
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sizeof(struct rte_tcp_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \
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sizeof(struct rte_udp_hdr) + \
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sizeof(struct rte_vxlan_hdr) + \
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sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_vlan_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \
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sizeof(struct rte_ipv6_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \
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sizeof(struct rte_tcp_hdr))
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/* Threshold of buffer replenishment for vectorized Rx. */
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#define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
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(RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
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/* Maximum size of burst for vectorized Rx. */
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#define MLX5_VPMD_RX_MAX_BURST 64U
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/* Number of packets vectorized Rx can simultaneously process in a loop. */
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#define MLX5_VPMD_DESCS_PER_LOOP 4
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/* Supported RSS */
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#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP))
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/* Timeout in seconds to get a valid link status. */
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#define MLX5_LINK_STATUS_TIMEOUT 10
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/* Maximum number of UAR pages used by a port,
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* These are the size and mask for an array of mutexes used to synchronize
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* the access to port's UARs on platforms that do not support 64 bit writes.
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* In such systems it is possible to issue the 64 bits DoorBells through two
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* consecutive writes, each write 32 bits. The access to a UAR page (which can
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* be accessible by all threads in the process) must be synchronized
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* (for example, using a semaphore). Such a synchronization is not required
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* when ringing DoorBells on different UAR pages.
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* A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared
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* among the ports.
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*/
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#define MLX5_UAR_PAGE_NUM_MAX 64
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#define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)
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/* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
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#define MLX5_MPRQ_STRIDE_NUM_N 6U
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/* Two-byte shift is disabled for Multi-Packet RQ. */
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#define MLX5_MPRQ_TWO_BYTE_SHIFT 0
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/*
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* Minimum size of packet to be memcpy'd instead of being attached as an
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* external buffer.
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*/
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#define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
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/* Minimum number Rx queues to enable Multi-Packet RQ. */
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#define MLX5_MPRQ_MIN_RXQS 12
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/* Cache size of mempool for Multi-Packet RQ. */
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#define MLX5_MPRQ_MP_CACHE_SZ 32U
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/* Definition of static_assert found in /usr/include/assert.h */
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#ifndef HAVE_STATIC_ASSERT
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#define static_assert _Static_assert
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#endif
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#endif /* RTE_PMD_MLX5_DEFS_H_ */
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