fc02b0bf7b
Update the SEU register definition. Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Signed-off-by: Andy Pei <andy.pei@intel.com> |
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.. | ||
osdep_raw | ||
osdep_rte | ||
ifpga_api.c | ||
ifpga_api.h | ||
ifpga_compat.h | ||
ifpga_defines.h | ||
ifpga_enumerate.c | ||
ifpga_enumerate.h | ||
ifpga_feature_dev.c | ||
ifpga_feature_dev.h | ||
ifpga_fme_dperf.c | ||
ifpga_fme_error.c | ||
ifpga_fme_iperf.c | ||
ifpga_fme_pr.c | ||
ifpga_fme.c | ||
ifpga_hw.h | ||
ifpga_port_error.c | ||
ifpga_port.c | ||
Makefile | ||
meson.build | ||
opae_at24_eeprom.c | ||
opae_at24_eeprom.h | ||
opae_debug.c | ||
opae_debug.h | ||
opae_eth_group.c | ||
opae_eth_group.h | ||
opae_hw_api.c | ||
opae_hw_api.h | ||
opae_i2c.c | ||
opae_i2c.h | ||
opae_ifpga_hw_api.c | ||
opae_ifpga_hw_api.h | ||
opae_intel_max10.c | ||
opae_intel_max10.h | ||
opae_osdep.h | ||
opae_spi_transaction.c | ||
opae_spi.c | ||
opae_spi.h | ||
README |
.. /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2010-2018 Intel Corporation */ Intel iFPGA driver ================== This directory contains source code of Intel FPGA driver released by the team which develops Intel FPGA Open Programmable Acceleration Engine (OPAE). The directory of base/ contains the original source package. The base code currently supports Intel FPGA solutions including integrated solution (Intel(R) Xeon(R) CPU with FPGAs) and discrete solution (Intel(R) Programmable Acceleration Card with Intel(R) Arria(R) 10 FPGA) and it could be extended to support more FPGA devices in the future. Please refer to [1][2] for more introduction on OPAE and Intel FPGAs. [1] https://01.org/OPAE [2] https://www.altera.com/solutions/acceleration-hub/overview.html Updating the driver =================== NOTE: The source code in this directory should not be modified apart from the following file(s): osdep_raw/osdep_generic.h osdep_rte/osdep_generic.h New Features ================== 2019-03: Support Intel FPGA PAC N3000 card. Some features added in this version: 1. Store private features in FME and Port list. 2. Add eth group devices driver. 3. Add altera SPI master driver and Intel MAX10 device driver. 4. Add Altera I2C master driver and AT24 eeprom driver. 5. Add Device Tree support to get the configuration from card. 6. Instruding and exposing APIs to DPDK PMD driver to access networking functionality.