9ceacab77a
TX confirmation mode provides dedicated confirmation queues for transmitted packets. These queues are used by software to get the status and release transmitted packets buffers. By default TX confirmation mode is kept disabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
186 lines
5.3 KiB
C
186 lines
5.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2016 NXP
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*
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*/
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#ifndef _DPAA2_ETHDEV_H
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#define _DPAA2_ETHDEV_H
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#include <rte_event_eth_rx_adapter.h>
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#include <rte_pmd_dpaa2.h>
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#include <dpaa2_hw_pvt.h>
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#include <mc/fsl_dpni.h>
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#include <mc/fsl_mc_sys.h>
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#define DPAA2_MIN_RX_BUF_SIZE 512
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#define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
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#define MAX_TCS DPNI_MAX_TC
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#define MAX_RX_QUEUES 128
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#define MAX_TX_QUEUES 16
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/*default tc to be used for ,congestion, distribution etc configuration. */
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#define DPAA2_DEF_TC 0
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/* Threshold for a Tx queue to *Enter* Congestion state.
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*/
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#define CONG_ENTER_TX_THRESHOLD 512
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/* Threshold for a queue to *Exit* Congestion state.
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*/
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#define CONG_EXIT_TX_THRESHOLD 480
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#define CONG_RETRY_COUNT 18000
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/* RX queue tail drop threshold
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* currently considering 64 KB packets
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*/
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#define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024)
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#define CONG_RX_OAL 128
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/* Size of the input SMMU mapped memory required by MC */
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#define DIST_PARAM_IOVA_SIZE 256
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/* Enable TX Congestion control support
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* default is disable
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*/
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#define DPAA2_TX_CGR_OFF 0x01
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/* Disable RX tail drop, default is enable */
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#define DPAA2_RX_TAILDROP_OFF 0x04
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#define DPAA2_RSS_OFFLOAD_ALL ( \
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ETH_RSS_L2_PAYLOAD | \
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ETH_RSS_IP | \
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ETH_RSS_UDP | \
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ETH_RSS_TCP | \
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ETH_RSS_SCTP)
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/* LX2 FRC Parsed values (Little Endian) */
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#define DPAA2_PKT_TYPE_ETHER 0x0060
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#define DPAA2_PKT_TYPE_IPV4 0x0000
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#define DPAA2_PKT_TYPE_IPV6 0x0020
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#define DPAA2_PKT_TYPE_IPV4_EXT \
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(0x0001 | DPAA2_PKT_TYPE_IPV4)
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#define DPAA2_PKT_TYPE_IPV6_EXT \
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(0x0001 | DPAA2_PKT_TYPE_IPV6)
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#define DPAA2_PKT_TYPE_IPV4_TCP \
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(0x000e | DPAA2_PKT_TYPE_IPV4)
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#define DPAA2_PKT_TYPE_IPV6_TCP \
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(0x000e | DPAA2_PKT_TYPE_IPV6)
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#define DPAA2_PKT_TYPE_IPV4_UDP \
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(0x0010 | DPAA2_PKT_TYPE_IPV4)
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#define DPAA2_PKT_TYPE_IPV6_UDP \
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(0x0010 | DPAA2_PKT_TYPE_IPV6)
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#define DPAA2_PKT_TYPE_IPV4_SCTP \
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(0x000f | DPAA2_PKT_TYPE_IPV4)
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#define DPAA2_PKT_TYPE_IPV6_SCTP \
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(0x000f | DPAA2_PKT_TYPE_IPV6)
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#define DPAA2_PKT_TYPE_IPV4_ICMP \
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(0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
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#define DPAA2_PKT_TYPE_IPV6_ICMP \
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(0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
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#define DPAA2_PKT_TYPE_VLAN_1 0x0160
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#define DPAA2_PKT_TYPE_VLAN_2 0x0260
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/* enable timestamp in mbuf*/
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extern enum pmd_dpaa2_ts dpaa2_enable_ts;
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#define DPAA2_QOS_TABLE_RECONFIGURE 1
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#define DPAA2_FS_TABLE_RECONFIGURE 2
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/*Externaly defined*/
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extern const struct rte_flow_ops dpaa2_flow_ops;
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extern enum rte_filter_type dpaa2_filter_type;
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struct dpaa2_dev_priv {
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void *hw;
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int32_t hw_id;
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int32_t qdid;
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uint16_t token;
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uint8_t nb_tx_queues;
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uint8_t nb_rx_queues;
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uint32_t options;
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void *rx_vq[MAX_RX_QUEUES];
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void *tx_vq[MAX_TX_QUEUES];
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struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
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void *tx_conf_vq[MAX_TX_QUEUES];
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uint8_t tx_conf_en;
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uint8_t max_mac_filters;
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uint8_t max_vlan_filters;
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uint8_t num_rx_tc;
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uint8_t flags; /*dpaa2 config flags */
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uint8_t en_ordered;
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uint8_t en_loose_ordered;
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uint8_t max_cgs;
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uint8_t cgid_in_use[MAX_RX_QUEUES];
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struct pattern_s {
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uint8_t item_count;
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uint8_t pattern_type[DPKG_MAX_NUM_OF_EXTRACTS];
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} pattern[MAX_TCS + 1];
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struct extract_s {
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struct dpkg_profile_cfg qos_key_cfg;
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struct dpkg_profile_cfg fs_key_cfg[MAX_TCS];
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uint64_t qos_extract_param;
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uint64_t fs_extract_param[MAX_TCS];
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} extract;
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LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
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};
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int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
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struct dpkg_profile_cfg *kg_cfg);
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int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
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uint64_t req_dist_set);
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int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
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uint8_t tc_index);
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int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
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int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
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int eth_rx_queue_id,
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uint16_t dpcon_id,
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const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
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int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
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int eth_rx_queue_id);
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uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
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uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
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uint16_t nb_pkts);
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uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
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uint16_t nb_pkts);
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void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
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const struct qbman_fd *fd,
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const struct qbman_result *dq,
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struct dpaa2_queue *rxq,
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struct rte_event *ev);
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void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
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const struct qbman_fd *fd,
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const struct qbman_result *dq,
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struct dpaa2_queue *rxq,
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struct rte_event *ev);
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void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
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const struct qbman_fd *fd,
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const struct qbman_result *dq,
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struct dpaa2_queue *rxq,
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struct rte_event *ev);
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uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
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uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
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uint16_t nb_pkts);
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uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
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void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
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void dpaa2_flow_clean(struct rte_eth_dev *dev);
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uint16_t dpaa2_dev_tx_conf(void *queue) __attribute__((unused));
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#endif /* _DPAA2_ETHDEV_H */
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