c1a320bf89
Currently, the PMD decides if the tunneling offload
can enable VXLAN/GRE/GENEVE tunneled TSO support by checking
config->tunnel_en (single bit) and config->tso.
This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload
DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload
DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload
DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled.
The fix enables the offloads according to the correct
flags returned by the kernel.
Fixes: dbccb4cddc ("net/mlx5: convert to new Tx offloads API")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Idan Hackmon <idanhac@nvidia.com>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2020 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_OS_H_
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#define RTE_PMD_MLX5_OS_H_
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#include <net/if.h>
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/* verb enumerations translations to local enums. */
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enum {
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MLX5_FS_NAME_MAX = IBV_SYSFS_NAME_MAX + 1,
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MLX5_FS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1
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};
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/* Maximal data of sendmsg message(in bytes). */
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#define MLX5_SENDMSG_MAX 64
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#define MLX5_NAMESIZE IF_NAMESIZE
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int mlx5_auxiliary_get_ifindex(const char *sf_name);
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enum mlx5_sw_parsing_offloads {
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#ifdef HAVE_IBV_MLX5_MOD_SWP
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MLX5_SW_PARSING_CAP = MLX5DV_SW_PARSING,
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MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,
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MLX5_SW_PARSING_TSO_CAP = MLX5DV_SW_PARSING_LSO,
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#else
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MLX5_SW_PARSING_CAP = 0,
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MLX5_SW_PARSING_CSUM_CAP = 0,
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MLX5_SW_PARSING_TSO_CAP = 0,
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#endif
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};
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enum mlx5_tunnel_offloads {
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#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
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MLX5_TUNNELED_OFFLOADS_VXLAN_CAP =
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MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN,
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MLX5_TUNNELED_OFFLOADS_GRE_CAP =
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MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE,
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MLX5_TUNNELED_OFFLOADS_GENEVE_CAP =
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MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE,
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#else
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MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0,
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MLX5_TUNNELED_OFFLOADS_GRE_CAP = 0,
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MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0,
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#endif
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};
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#endif /* RTE_PMD_MLX5_OS_H_ */
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