bab97a3ffb
CN98xx SoC comes up with two CPT blocks wrt CN96xx, CN93xx, to achieve higher performance. Adding support to allocate all LFs of VF with even BDF from CPT0 and all LFs of VF with odd BDF from CPT1. If LFs are not available in one block then they will be allocated from alternate block. Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Acked-by: Anoob Joseph <anoobj@marvell.com>
162 lines
4.2 KiB
C
162 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_
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#define _OTX2_CRYPTODEV_HW_ACCESS_H_
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#include <stdint.h>
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#include <rte_cryptodev.h>
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#include <rte_memory.h>
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#include "cpt_common.h"
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#include "cpt_hw_types.h"
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#include "cpt_mcode_defines.h"
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#include "otx2_dev.h"
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#include "otx2_cryptodev_qp.h"
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/* CPT instruction queue length */
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#define OTX2_CPT_IQ_LEN 8200
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#define OTX2_CPT_DEFAULT_CMD_QLEN OTX2_CPT_IQ_LEN
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/* Mask which selects all engine groups */
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#define OTX2_CPT_ENG_GRPS_MASK 0xFF
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/* Register offsets */
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/* LMT LF registers */
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#define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3)
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/* CPT LF registers */
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#define OTX2_CPT_LF_CTL 0x10ull
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#define OTX2_CPT_LF_INPROG 0x40ull
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#define OTX2_CPT_LF_MISC_INT 0xb0ull
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#define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull
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#define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull
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#define OTX2_CPT_LF_Q_BASE 0xf0ull
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#define OTX2_CPT_LF_Q_SIZE 0x100ull
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#define OTX2_CPT_LF_Q_GRP_PTR 0x120ull
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#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3)
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#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
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#define OTX2_CPT_AF_LF_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
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#define OTX2_CPT_LF_BAR2(vf, blk_addr, q_id) \
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((vf)->otx2_dev.bar2 + \
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((blk_addr << 20) | ((q_id) << 12)))
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#define OTX2_CPT_QUEUE_HI_PRIO 0x1
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union otx2_cpt_lf_ctl {
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uint64_t u;
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struct {
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uint64_t ena : 1;
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uint64_t fc_ena : 1;
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uint64_t fc_up_crossing : 1;
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uint64_t reserved_3_3 : 1;
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uint64_t fc_hyst_bits : 4;
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uint64_t reserved_8_63 : 56;
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} s;
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};
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union otx2_cpt_lf_inprog {
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uint64_t u;
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struct {
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uint64_t inflight : 9;
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uint64_t reserved_9_15 : 7;
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uint64_t eena : 1;
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uint64_t grp_drp : 1;
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uint64_t reserved_18_30 : 13;
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uint64_t grb_partial : 1;
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uint64_t grb_cnt : 8;
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uint64_t gwb_cnt : 8;
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uint64_t reserved_48_63 : 16;
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} s;
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};
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union otx2_cpt_lf_q_base {
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uint64_t u;
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struct {
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uint64_t fault : 1;
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uint64_t stopped : 1;
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uint64_t reserved_2_6 : 5;
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uint64_t addr : 46;
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uint64_t reserved_53_63 : 11;
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} s;
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};
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union otx2_cpt_lf_q_size {
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uint64_t u;
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struct {
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uint64_t size_div40 : 15;
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uint64_t reserved_15_63 : 49;
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} s;
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};
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union otx2_cpt_af_lf_ctl {
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uint64_t u;
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struct {
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uint64_t pri : 1;
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uint64_t reserved_1_8 : 8;
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uint64_t pf_func_inst : 1;
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uint64_t cont_err : 1;
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uint64_t reserved_11_15 : 5;
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uint64_t nixtx_en : 1;
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uint64_t reserved_17_47 : 31;
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uint64_t grp : 8;
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uint64_t reserved_56_63 : 8;
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} s;
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};
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union otx2_cpt_af_lf_ctl2 {
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uint64_t u;
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struct {
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uint64_t exe_no_swap : 1;
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uint64_t exe_ldwb : 1;
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uint64_t reserved_2_31 : 30;
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uint64_t sso_pf_func : 16;
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uint64_t nix_pf_func : 16;
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} s;
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};
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union otx2_cpt_lf_q_grp_ptr {
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uint64_t u;
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struct {
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uint64_t dq_ptr : 15;
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uint64_t reserved_31_15 : 17;
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uint64_t nq_ptr : 15;
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uint64_t reserved_47_62 : 16;
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uint64_t xq_xor : 1;
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} s;
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};
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/*
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* Enumeration cpt_9x_comp_e
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*
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* CPT 9X Completion Enumeration
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* Enumerates the values of CPT_RES_S[COMPCODE].
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*/
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enum cpt_9x_comp_e {
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CPT_9X_COMP_E_NOTDONE = 0x00,
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CPT_9X_COMP_E_GOOD = 0x01,
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CPT_9X_COMP_E_FAULT = 0x02,
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CPT_9X_COMP_E_HWERR = 0x04,
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CPT_9X_COMP_E_INSTERR = 0x05,
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CPT_9X_COMP_E_LAST_ENTRY = 0x06
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};
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void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);
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int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);
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int otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
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const struct otx2_cpt_qp *qp, uint8_t grp_mask,
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uint8_t pri, uint32_t size_div40);
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void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp);
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#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */
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