2f89dc2ed7
Volatile has no ordering semantics. The rte_timer structure defines timer status as a volatile variable and uses the rte_r/wmb barrier to guarantee inter-thread visibility. This patch optimized the volatile operation with c11 atomic operations and one-way barrier to save the performance penalty. According to the timer_perf_autotest benchmarking results, this patch can uplift 10%~16% timer appending performance, 3%~20% timer resetting performance and 45% timer callbacks scheduling performance on aarch64 and no loss in performance for x86. Suggested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Signed-off-by: Phil Yang <phil.yang@arm.com> Reviewed-by: Gavin Hu <gavin.hu@arm.com> Acked-by: Erik Gabriel Carrillo <erik.g.carrillo@intel.com> |
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| .. | ||
| Makefile | ||
| meson.build | ||
| rte_timer_version.map | ||
| rte_timer.c | ||
| rte_timer.h | ||