94131e4ab7
During some fatal firmware error conditions, the PCI config space
register 0x2e which normally contains the subsystem ID will become
0xffff. This register will revert back to the normal value after
the chip has completed core reset. If we detect this condition,
we can poll this config register immediately for the value to revert.
Because we use config read cycles to poll this register, there is no
possibility of Master Abort if we happen to read it during core reset.
This speeds up recovery significantly as we don't have to wait for the
conservative min_time before polling to see if the firmware has come
out of reset. As soon as this register changes value we can proceed
to re-initialize the device.
Fixes: df6cd7c1f7 ("net/bnxt: handle reset notify async event from FW")
Cc: stable@dpdk.org
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
19 lines
381 B
C
19 lines
381 B
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2021 Broadcom
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* All rights reserved.
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*/
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#ifndef _BNXT_UTIL_H_
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#define _BNXT_UTIL_H_
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#ifndef BIT
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#define BIT(n) (1UL << (n))
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#endif /* BIT */
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#define PCI_SUBSYSTEM_ID_OFFSET 0x2e
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int bnxt_check_zero_bytes(const uint8_t *bytes, int len);
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void bnxt_eth_hw_addr_random(uint8_t *mac_addr);
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#endif /* _BNXT_UTIL_H_ */
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