a4e6ea97a5
In function mlx5_devx_cmd_create_tir(), the 40 bytes of RSS key are
copied in 10 iterations, 4 bytes each time using the MLX5_SET macro.
As result the RSS key is copied into TIR context in swapped byte order.
This patch fixes the issue, using memcpy() to copy the RSS key as is.
The struct member mlx5_devx_tir_attr.rx_hash_toeplitz_key is updated
to byte array type.
Fixes: c3aea272ee ("net/mlx5: create advanced Rx object via DevX")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
353 lines
10 KiB
C
353 lines
10 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2019 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
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#define RTE_PMD_MLX5_DEVX_CMDS_H_
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#include "mlx5_glue.h"
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#include "mlx5_prm.h"
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/* devX creation object */
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struct mlx5_devx_obj {
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struct mlx5dv_devx_obj *obj; /* The DV object. */
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int id; /* The object ID. */
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};
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/* UMR memory buffer used to define 1 entry in indirect mkey. */
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struct mlx5_klm {
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uint32_t byte_count;
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uint32_t mkey;
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uint64_t address;
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};
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/* This is limitation of libibverbs: in length variable type is u16. */
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#define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
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MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
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struct mlx5_devx_mkey_attr {
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uint64_t addr;
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uint64_t size;
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uint32_t umem_id;
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uint32_t pd;
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uint32_t log_entity_size;
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uint32_t pg_access:1;
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uint32_t relaxed_ordering:1;
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struct mlx5_klm *klm_array;
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int klm_num;
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};
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/* HCA qos attributes. */
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struct mlx5_hca_qos_attr {
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uint32_t sup:1; /* Whether QOS is supported. */
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uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
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uint32_t flow_meter_reg_share:1;
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/* Whether reg_c share is supported. */
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uint8_t log_max_flow_meter;
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/* Power of the maximum supported meters. */
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uint8_t flow_meter_reg_c_ids;
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/* Bitmap of the reg_Cs available for flow meter to use. */
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};
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struct mlx5_hca_vdpa_attr {
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uint8_t virtio_queue_type;
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uint32_t valid:1;
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uint32_t desc_tunnel_offload_type:1;
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uint32_t eth_frame_offload_type:1;
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uint32_t virtio_version_1_0:1;
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uint32_t tso_ipv4:1;
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uint32_t tso_ipv6:1;
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uint32_t tx_csum:1;
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uint32_t rx_csum:1;
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uint32_t event_mode:3;
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uint32_t log_doorbell_stride:5;
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uint32_t log_doorbell_bar_size:5;
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uint32_t max_num_virtio_queues;
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struct {
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uint32_t a;
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uint32_t b;
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} umems[3];
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uint64_t doorbell_bar_offset;
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};
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/* HCA supports this number of time periods for LRO. */
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#define MLX5_LRO_NUM_SUPP_PERIODS 4
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/* HCA attributes. */
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struct mlx5_hca_attr {
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uint32_t eswitch_manager:1;
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uint32_t flow_counters_dump:1;
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uint32_t log_max_rqt_size:5;
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uint8_t flow_counter_bulk_alloc_bitmap;
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uint32_t eth_net_offloads:1;
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uint32_t eth_virt:1;
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uint32_t wqe_vlan_insert:1;
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uint32_t wqe_inline_mode:2;
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uint32_t vport_inline_mode:3;
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uint32_t tunnel_stateless_geneve_rx:1;
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uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
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uint32_t tunnel_stateless_gtp:1;
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uint32_t lro_cap:1;
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uint32_t tunnel_lro_gre:1;
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uint32_t tunnel_lro_vxlan:1;
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uint32_t lro_max_msg_sz_mode:2;
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uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
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uint32_t flex_parser_protocols;
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uint32_t hairpin:1;
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uint32_t log_max_hairpin_queues:5;
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uint32_t log_max_hairpin_wq_data_sz:5;
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uint32_t log_max_hairpin_num_packets:5;
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uint32_t vhca_id:16;
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struct mlx5_hca_qos_attr qos;
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struct mlx5_hca_vdpa_attr vdpa;
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};
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struct mlx5_devx_wq_attr {
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uint32_t wq_type:4;
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uint32_t wq_signature:1;
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uint32_t end_padding_mode:2;
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uint32_t cd_slave:1;
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uint32_t hds_skip_first_sge:1;
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uint32_t log2_hds_buf_size:3;
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uint32_t page_offset:5;
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uint32_t lwm:16;
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uint32_t pd:24;
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uint32_t uar_page:24;
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uint64_t dbr_addr;
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uint32_t hw_counter;
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uint32_t sw_counter;
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uint32_t log_wq_stride:4;
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uint32_t log_wq_pg_sz:5;
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uint32_t log_wq_sz:5;
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uint32_t dbr_umem_valid:1;
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uint32_t wq_umem_valid:1;
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uint32_t log_hairpin_num_packets:5;
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uint32_t log_hairpin_data_sz:5;
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uint32_t single_wqe_log_num_of_strides:4;
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uint32_t two_byte_shift_en:1;
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uint32_t single_stride_log_num_of_bytes:3;
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uint32_t dbr_umem_id;
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uint32_t wq_umem_id;
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uint64_t wq_umem_offset;
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};
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/* Create RQ attributes structure, used by create RQ operation. */
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struct mlx5_devx_create_rq_attr {
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uint32_t rlky:1;
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uint32_t delay_drop_en:1;
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uint32_t scatter_fcs:1;
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uint32_t vsd:1;
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uint32_t mem_rq_type:4;
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uint32_t state:4;
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uint32_t flush_in_error_en:1;
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uint32_t hairpin:1;
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uint32_t user_index:24;
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uint32_t cqn:24;
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uint32_t counter_set_id:8;
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uint32_t rmpn:24;
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struct mlx5_devx_wq_attr wq_attr;
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};
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/* Modify RQ attributes structure, used by modify RQ operation. */
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struct mlx5_devx_modify_rq_attr {
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uint32_t rqn:24;
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uint32_t rq_state:4; /* Current RQ state. */
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uint32_t state:4; /* Required RQ state. */
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uint32_t scatter_fcs:1;
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uint32_t vsd:1;
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uint32_t counter_set_id:8;
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uint32_t hairpin_peer_sq:24;
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uint32_t hairpin_peer_vhca:16;
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uint64_t modify_bitmask;
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uint32_t lwm:16; /* Contained WQ lwm. */
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};
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struct mlx5_rx_hash_field_select {
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uint32_t l3_prot_type:1;
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uint32_t l4_prot_type:1;
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uint32_t selected_fields:30;
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};
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/* TIR attributes structure, used by TIR operations. */
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struct mlx5_devx_tir_attr {
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uint32_t disp_type:4;
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uint32_t lro_timeout_period_usecs:16;
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uint32_t lro_enable_mask:4;
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uint32_t lro_max_msg_sz:8;
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uint32_t inline_rqn:24;
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uint32_t rx_hash_symmetric:1;
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uint32_t tunneled_offload_en:1;
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uint32_t indirect_table:24;
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uint32_t rx_hash_fn:4;
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uint32_t self_lb_block:2;
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uint32_t transport_domain:24;
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uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
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struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
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struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
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};
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/* RQT attributes structure, used by RQT operations. */
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struct mlx5_devx_rqt_attr {
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uint8_t rq_type;
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uint32_t rqt_max_size:16;
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uint32_t rqt_actual_size:16;
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uint32_t rq_list[];
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};
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/* TIS attributes structure. */
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struct mlx5_devx_tis_attr {
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uint32_t strict_lag_tx_port_affinity:1;
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uint32_t tls_en:1;
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uint32_t lag_tx_port_affinity:4;
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uint32_t prio:4;
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uint32_t transport_domain:24;
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};
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/* SQ attributes structure, used by SQ create operation. */
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struct mlx5_devx_create_sq_attr {
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uint32_t rlky:1;
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uint32_t cd_master:1;
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uint32_t fre:1;
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uint32_t flush_in_error_en:1;
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uint32_t allow_multi_pkt_send_wqe:1;
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uint32_t min_wqe_inline_mode:3;
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uint32_t state:4;
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uint32_t reg_umr:1;
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uint32_t allow_swp:1;
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uint32_t hairpin:1;
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uint32_t user_index:24;
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uint32_t cqn:24;
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uint32_t packet_pacing_rate_limit_index:16;
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uint32_t tis_lst_sz:16;
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uint32_t tis_num:24;
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struct mlx5_devx_wq_attr wq_attr;
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};
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/* SQ attributes structure, used by SQ modify operation. */
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struct mlx5_devx_modify_sq_attr {
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uint32_t sq_state:4;
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uint32_t state:4;
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uint32_t hairpin_peer_rq:24;
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uint32_t hairpin_peer_vhca:16;
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};
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/* CQ attributes structure, used by CQ operations. */
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struct mlx5_devx_cq_attr {
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uint32_t q_umem_valid:1;
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uint32_t db_umem_valid:1;
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uint32_t use_first_only:1;
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uint32_t overrun_ignore:1;
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uint32_t log_cq_size:5;
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uint32_t log_page_size:5;
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uint32_t uar_page_id;
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uint32_t q_umem_id;
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uint64_t q_umem_offset;
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uint32_t db_umem_id;
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uint64_t db_umem_offset;
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uint32_t eqn;
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uint64_t db_addr;
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};
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/* Virtq attributes structure, used by VIRTQ operations. */
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struct mlx5_devx_virtq_attr {
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uint16_t hw_available_index;
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uint16_t hw_used_index;
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uint16_t q_size;
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uint32_t virtio_version_1_0:1;
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uint32_t tso_ipv4:1;
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uint32_t tso_ipv6:1;
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uint32_t tx_csum:1;
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uint32_t rx_csum:1;
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uint32_t event_mode:3;
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uint32_t state:4;
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uint32_t dirty_bitmap_dump_enable:1;
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uint32_t dirty_bitmap_mkey;
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uint32_t dirty_bitmap_size;
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uint32_t mkey;
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uint32_t qp_id;
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uint32_t queue_index;
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uint32_t tis_id;
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uint64_t dirty_bitmap_addr;
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uint64_t type;
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uint64_t desc_addr;
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uint64_t used_addr;
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uint64_t available_addr;
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struct {
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uint32_t id;
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uint32_t size;
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uint64_t offset;
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} umems[3];
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};
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struct mlx5_devx_qp_attr {
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uint32_t pd:24;
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uint32_t uar_index:24;
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uint32_t cqn:24;
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uint32_t log_page_size:5;
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uint32_t rq_size:17; /* Must be power of 2. */
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uint32_t log_rq_stride:3;
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uint32_t sq_size:17; /* Must be power of 2. */
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uint32_t dbr_umem_valid:1;
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uint32_t dbr_umem_id;
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uint64_t dbr_address;
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uint32_t wq_umem_id;
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uint64_t wq_umem_offset;
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};
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/* mlx5_devx_cmds.c */
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struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
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uint32_t bulk_sz);
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int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
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int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
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int clear, uint32_t n_counters,
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uint64_t *pkts, uint64_t *bytes,
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uint32_t mkey, void *addr,
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struct mlx5dv_devx_cmd_comp *cmd_comp,
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uint64_t async_id);
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int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
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struct mlx5_hca_attr *attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
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struct mlx5_devx_mkey_attr *attr);
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int mlx5_devx_get_out_command_status(void *out);
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int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
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uint32_t *tis_td);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
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struct mlx5_devx_create_rq_attr *rq_attr,
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int socket);
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int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
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struct mlx5_devx_modify_rq_attr *rq_attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
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struct mlx5_devx_tir_attr *tir_attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
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struct mlx5_devx_rqt_attr *rqt_attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
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struct mlx5_devx_create_sq_attr *sq_attr);
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int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
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struct mlx5_devx_modify_sq_attr *sq_attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
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struct mlx5_devx_tis_attr *tis_attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
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int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
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FILE *file);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(struct ibv_context *ctx,
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struct mlx5_devx_cq_attr *attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(struct ibv_context *ctx,
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struct mlx5_devx_virtq_attr *attr);
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int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
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struct mlx5_devx_virtq_attr *attr);
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int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
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struct mlx5_devx_virtq_attr *attr);
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struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(struct ibv_context *ctx,
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struct mlx5_devx_qp_attr *attr);
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int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
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uint32_t qp_st_mod_op, uint32_t remote_qp_id);
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int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
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struct mlx5_devx_rqt_attr *rqt_attr);
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#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
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