a45859312f
Microcode SE opcodes support symmetric operations. Add defines and structs defined by microcode. Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
125 lines
2.6 KiB
C
125 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _ROC_API_H_
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#define _ROC_API_H_
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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/* Alignment */
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#define ROC_ALIGN 128
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/* Bits manipulation */
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#include "roc_bits.h"
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/* Bitfields manipulation */
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#include "roc_bitfield.h"
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/* Constants */
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#define PLT_ETHER_ADDR_LEN 6
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/* Platform definition */
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#include "roc_platform.h"
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#define ROC_LMT_LINE_SZ 128
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#define ROC_NUM_LMT_LINES 2048
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#define ROC_LMT_LINES_PER_CORE_LOG2 5
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#define ROC_LMT_LINE_SIZE_LOG2 7
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#define ROC_LMT_BASE_PER_CORE_LOG2 \
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(ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2)
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/* IO */
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#if defined(__aarch64__)
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#include "roc_io.h"
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#else
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#include "roc_io_generic.h"
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#endif
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/* PCI IDs */
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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#define PCI_DEVID_CNXK_RVU_PF 0xA063
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#define PCI_DEVID_CNXK_RVU_VF 0xA064
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#define PCI_DEVID_CNXK_RVU_AF 0xA065
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#define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9
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#define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA
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#define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB
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#define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC
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#define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8
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#define PCI_DEVID_CNXK_DPI_VF 0xA081
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#define PCI_DEVID_CNXK_EP_VF 0xB203
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#define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6
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#define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7
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#define PCI_DEVID_CNXK_BPHY 0xA089
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#define PCI_DEVID_CN9K_CGX 0xA059
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#define PCI_DEVID_CN10K_RPM 0xA060
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#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD
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#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE
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#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2
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#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3
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#define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900
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#define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
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#define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000
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#define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400
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#define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200
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#define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200
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#define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
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/* HW structure definition */
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#include "hw/cpt.h"
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#include "hw/nix.h"
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#include "hw/npa.h"
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#include "hw/npc.h"
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#include "hw/rvu.h"
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#include "hw/sdp.h"
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#include "hw/sso.h"
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#include "hw/ssow.h"
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#include "hw/tim.h"
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/* Model */
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#include "roc_model.h"
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/* Mbox */
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#include "roc_mbox.h"
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/* NPA */
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#include "roc_npa.h"
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/* NPC */
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#include "roc_npc.h"
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/* NIX */
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#include "roc_nix.h"
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/* SSO */
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#include "roc_sso.h"
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/* TIM */
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#include "roc_tim.h"
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/* Utils */
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#include "roc_utils.h"
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/* Idev */
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#include "roc_idev.h"
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/* Baseband phy cgx */
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#include "roc_bphy_cgx.h"
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/* Baseband phy */
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#include "roc_bphy.h"
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/* CPT */
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#include "roc_cpt.h"
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/* CPT microcode */
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#include "roc_se.h"
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#endif /* _ROC_API_H_ */
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