a5aeb2b9e2
Below ops are added too: mac_addr_add mac_addr_remove mac_addr_set set_mc_addr_list mtu_set promiscuous_enable promiscuous_disable allmulticast_enable allmulticast_disable rx_queue_setup rx_queue_release rx_queue_count rx_descriptor_done rx_descriptor_status tx_descriptor_status tx_queue_setup tx_queue_release tx_done_cleanup rxq_info_get txq_info_get dev_supported_ptypes_get Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
135 lines
3.2 KiB
C
135 lines
3.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019-2020 Intel Corporation
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*/
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#ifndef _IGC_ETHDEV_H_
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#define _IGC_ETHDEV_H_
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#include <rte_ethdev.h>
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#include "base/igc_osdep.h"
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#include "base/igc_hw.h"
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#include "base/igc_i225.h"
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#include "base/igc_api.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define IGC_QUEUE_PAIRS_NUM 4
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#define IGC_HKEY_MAX_INDEX 10
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#define IGC_RSS_RDT_SIZD 128
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
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* This will also optimize cache line size effect.
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* H/W supports up to cache line size 128.
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*/
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#define IGC_ALIGN 128
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#define IGC_TX_DESCRIPTOR_MULTIPLE 8
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#define IGC_RX_DESCRIPTOR_MULTIPLE 8
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#define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
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sizeof(union igc_adv_rx_desc)))
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#define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
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sizeof(union igc_adv_tx_desc)))
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#define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
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#define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
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#define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
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#define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
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#define IGC_TX_MAX_SEG UINT8_MAX
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#define IGC_TX_MAX_MTU_SEG UINT8_MAX
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#define IGC_RX_OFFLOAD_ALL ( \
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DEV_RX_OFFLOAD_IPV4_CKSUM | \
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DEV_RX_OFFLOAD_UDP_CKSUM | \
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DEV_RX_OFFLOAD_TCP_CKSUM | \
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DEV_RX_OFFLOAD_SCTP_CKSUM | \
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DEV_RX_OFFLOAD_JUMBO_FRAME | \
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DEV_RX_OFFLOAD_KEEP_CRC | \
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DEV_RX_OFFLOAD_SCATTER)
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#define IGC_TX_OFFLOAD_ALL ( \
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DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_UDP_TSO | \
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DEV_TX_OFFLOAD_MULTI_SEGS)
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#define IGC_RSS_OFFLOAD_ALL ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_IPV6_EX | \
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ETH_RSS_IPV6_TCP_EX | \
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ETH_RSS_IPV6_UDP_EX)
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/* structure for interrupt relative data */
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struct igc_interrupt {
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uint32_t flags;
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uint32_t mask;
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};
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/* Union of RSS redirect table register */
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union igc_rss_reta_reg {
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uint32_t dword;
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uint8_t bytes[4];
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};
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/*
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* Structure to store private data for each driver instance (for each port).
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*/
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struct igc_adapter {
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struct igc_hw hw;
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struct igc_interrupt intr;
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bool stopped;
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};
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#define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
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#define IGC_DEV_PRIVATE_HW(_dev) \
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(&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
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#define IGC_DEV_PRIVATE_INTR(_dev) \
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(&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
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static inline void
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igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
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{
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uint32_t reg_val = IGC_READ_REG(hw, reg);
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bits |= reg_val;
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if (bits == reg_val)
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return; /* no need to write back */
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IGC_WRITE_REG(hw, reg, bits);
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}
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static inline void
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igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
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{
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uint32_t reg_val = IGC_READ_REG(hw, reg);
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bits = reg_val & ~bits;
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if (bits == reg_val)
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return; /* no need to write back */
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IGC_WRITE_REG(hw, reg, bits);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _IGC_ETHDEV_H_ */
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