03c8f2fe11
There is a rare hardware bug that can cause a bad opaque value in the RX
or TPA start completion. When this happens, the hardware may have used the
same buffer twice for 2 Rx packets. In addition, the driver might also
crash later using the bad opaque as an index into the ring.
The Rx opaque value is predictable and is always monotonically increasing.
The workaround is to keep track of the expected next opaque value and
compare it with the one returned by hardware during RX and TPA start
completions. If they miscompare, log it, discard the completion,
schedule a ring reset and move on to the next one.
Fixes: 0958d8b643 ("net/bnxt: support LRO")
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2021 Broadcom
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* All rights reserved.
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*/
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#ifndef _BNXT_RQX_H_
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#define _BNXT_RQX_H_
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/* Maximum receive burst supported in vector mode. */
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#define RTE_BNXT_MAX_RX_BURST 64U
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/* Drop by default when receive desc is not available. */
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#define BNXT_DEFAULT_RX_DROP_EN 1
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struct bnxt;
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struct bnxt_rx_ring_info;
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struct bnxt_cp_ring_info;
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struct bnxt_rx_queue {
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struct rte_mempool *mb_pool; /* mbuf pool for RX ring */
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uint64_t mbuf_initializer; /* val to init mbuf */
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uint16_t nb_rx_desc; /* num of RX desc */
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uint16_t rx_free_thresh; /* max free RX desc to hold */
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uint16_t queue_id; /* RX queue index */
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#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
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uint16_t rxrearm_nb; /* number of descs to reinit. */
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uint16_t rxrearm_start; /* next desc index to reinit. */
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#endif
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uint16_t port_id; /* Device port identifier */
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uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
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uint8_t rx_deferred_start; /* not in global dev start */
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uint8_t rx_started; /* RX queue is started */
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uint8_t drop_en; /* Drop when rx desc not available. */
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uint8_t in_reset; /* Rx ring is scheduled for reset */
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struct bnxt *bp;
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int index;
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struct bnxt_vnic_info *vnic;
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uint32_t rx_buf_size;
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struct bnxt_rx_ring_info *rx_ring;
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struct bnxt_cp_ring_info *cp_ring;
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struct rte_mbuf fake_mbuf;
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rte_atomic64_t rx_mbuf_alloc_fail;
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const struct rte_memzone *mz;
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};
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void bnxt_free_rxq_stats(struct bnxt_rx_queue *rxq);
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int bnxt_mq_rx_configure(struct bnxt *bp);
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void bnxt_rx_queue_release_op(void *rx_queue);
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int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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void bnxt_free_rx_mbufs(struct bnxt *bp);
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int bnxt_rx_queue_intr_enable_op(struct rte_eth_dev *eth_dev,
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uint16_t queue_id);
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int bnxt_rx_queue_intr_disable_op(struct rte_eth_dev *eth_dev,
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uint16_t queue_id);
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int bnxt_rx_queue_start(struct rte_eth_dev *dev,
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uint16_t rx_queue_id);
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int bnxt_rx_queue_stop(struct rte_eth_dev *dev,
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uint16_t rx_queue_id);
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void bnxt_rx_queue_release_mbufs(struct bnxt_rx_queue *rxq);
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#endif
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