797ce8eec7
Management firmware does not properly clean IGU block in PF FLR flow
which may result in undelivered attentions for link events from
default status block.
Add a workaround in PMD to execute extra IGU cleanup right after PF FLR
is done.
Fixes: 9e2f08a4ad ("net/qede/base: add request for PF FLR before load request")
Cc: stable@dpdk.org
Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
262 lines
6.5 KiB
C
262 lines
6.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2016 - 2018 Cavium Inc.
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* All rights reserved.
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* www.cavium.com
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*/
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#ifndef __ECORE_INT_H__
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#define __ECORE_INT_H__
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#include "ecore.h"
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#include "ecore_int_api.h"
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#define ECORE_CAU_DEF_RX_TIMER_RES 0
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#define ECORE_CAU_DEF_TX_TIMER_RES 0
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#define ECORE_SB_ATT_IDX 0x0001
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#define ECORE_SB_EVENT_MASK 0x0003
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#define SB_ALIGNED_SIZE(p_hwfn) \
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ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
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#define ECORE_SB_INVALID_IDX 0xffff
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struct ecore_igu_block {
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u8 status;
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#define ECORE_IGU_STATUS_FREE 0x01
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#define ECORE_IGU_STATUS_VALID 0x02
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#define ECORE_IGU_STATUS_PF 0x04
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#define ECORE_IGU_STATUS_DSB 0x08
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u8 vector_number;
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u8 function_id;
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u8 is_pf;
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/* Index inside IGU [meant for back reference] */
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u16 igu_sb_id;
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struct ecore_sb_info *sb_info;
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};
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struct ecore_igu_info {
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struct ecore_igu_block entry[MAX_TOT_SB_PER_PATH];
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u16 igu_dsb_id;
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/* The numbers can shift when using APIs to switch SBs between PF and
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* VF.
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*/
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struct ecore_sb_cnt_info usage;
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/* Determine whether we can shift SBs between VFs and PFs */
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bool b_allow_pf_vf_change;
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};
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/**
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* @brief - Make sure the IGU CAM reflects the resources provided by MFW
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*
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* @param p_hwfn
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* @param p_ptt
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*/
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int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt);
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/**
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* @brief - Make sure IGU CAM reflects the default resources once again,
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* starting with a 'dirty' SW database.
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* @param p_hwfn
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* @param p_ptt
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*/
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int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt);
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/**
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* @brief Translate the weakly-defined client sb-id into an IGU sb-id
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*
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* @param p_hwfn
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* @param sb_id - user provided sb_id
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*
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* @return an index inside IGU CAM where the SB resides
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*/
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u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id);
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/**
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* @brief return a pointer to an unused valid SB
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*
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* @param p_hwfn
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* @param b_is_pf - true iff we want a SB belonging to a PF
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*
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* @return point to an igu_block, OSAL_NULL if none is available
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*/
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struct ecore_igu_block *
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ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf);
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/* TODO Names of function may change... */
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void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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bool b_set, bool b_slowpath);
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void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_int_igu_read_cam - Reads the IGU CAM.
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* This function needs to be called during hardware
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* prepare. It reads the info from igu cam to know which
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* status block is the default / base status block etc.
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return enum _ecore_status_t
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*/
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enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt);
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typedef enum _ecore_status_t (*ecore_int_comp_cb_t) (struct ecore_hwfn *p_hwfn,
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void *cookie);
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/**
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* @brief ecore_int_register_cb - Register callback func for
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* slowhwfn statusblock.
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*
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* Every protocol that uses the slowhwfn status block
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* should register a callback function that will be called
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* once there is an update of the sp status block.
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*
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* @param p_hwfn
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* @param comp_cb - function to be called when there is an
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* interrupt on the sp sb
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*
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* @param cookie - passed to the callback function
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* @param sb_idx - OUT parameter which gives the chosen index
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* for this protocol.
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* @param p_fw_cons - pointer to the actual address of the
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* consumer for this protocol.
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*
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* @return enum _ecore_status_t
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*/
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enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
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ecore_int_comp_cb_t comp_cb,
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void *cookie,
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u8 *sb_idx, __le16 **p_fw_cons);
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/**
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* @brief ecore_int_unregister_cb - Unregisters callback
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* function from sp sb.
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* Partner of ecore_int_register_cb -> should be called
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* when no longer required.
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*
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* @param p_hwfn
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* @param pi
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*
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* @return enum _ecore_status_t
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*/
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enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi);
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/**
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* @brief ecore_int_get_sp_sb_id - Get the slowhwfn sb id.
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*
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* @param p_hwfn
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*
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* @return u16
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*/
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u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn);
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/**
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* @brief Status block cleanup. Should be called for each status
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* block that will be used -> both PF / VF
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*
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* @param p_hwfn
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* @param p_ptt
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* @param sb_id - igu status block id
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* @param opaque - opaque fid of the sb owner.
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* @param cleanup_set - set(1) / clear(0)
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*/
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void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u16 sb_id,
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u16 opaque,
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bool b_set);
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/**
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* @brief ecore_int_cau_conf - configure cau for a given status
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* block
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*
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* @param p_hwfn
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* @param ptt
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* @param sb_phys
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* @param igu_sb_id
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* @param vf_number
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* @param vf_valid
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*/
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void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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dma_addr_t sb_phys,
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u16 igu_sb_id, u16 vf_number, u8 vf_valid);
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/**
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* @brief ecore_int_alloc
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return enum _ecore_status_t
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*/
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enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt);
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/**
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* @brief ecore_int_free
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*
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* @param p_hwfn
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*/
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void ecore_int_free(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_int_setup
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*
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* @param p_hwfn
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* @param p_ptt
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*/
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void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
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/**
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* @brief - Enable Interrupt & Attention for hw function
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*
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* @param p_hwfn
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* @param p_ptt
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* @param int_mode
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*
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* @return enum _ecore_status_t
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*/
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enum _ecore_status_t ecore_int_igu_enable(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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enum ecore_int_mode int_mode);
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/**
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* @brief - Initialize CAU status block entry
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*
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* @param p_hwfn
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* @param p_sb_entry
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* @param pf_id
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* @param vf_number
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* @param vf_valid
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*/
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void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
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struct cau_sb_entry *p_sb_entry, u8 pf_id,
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u16 vf_number, u8 vf_valid);
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enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u8 timer_res, u16 sb_id, bool tx);
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#ifndef ASIC_ONLY
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#define ECORE_MAPPING_MEMORY_SIZE(dev) \
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((CHIP_REV_IS_SLOW(dev) && (!(dev)->b_is_emul_full)) ? \
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136 : NUM_OF_SBS(dev))
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#else
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#define ECORE_MAPPING_MEMORY_SIZE(dev) NUM_OF_SBS(dev)
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#endif
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enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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bool is_hw_init);
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void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn);
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#endif /* __ECORE_INT_H__ */
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