abf7275bba
move ixgbe PMD to drivers/net directory. As part of the move, we rename the ixgbe directory, containing the ixgbe "base driver" code, from "ixgbe" to "base". Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: John McNamara <john.mcnamara@intel.com> Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
300 lines
8.5 KiB
C
300 lines
8.5 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IXGBE_BYPASS_API_H_
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#define _IXGBE_BYPASS_API_H_
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#ifdef RTE_NIC_BYPASS
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#include "ixgbe_bypass_defines.h"
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/**
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* ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
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*
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* @hw: pointer to hardware structure
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* @cmd: Command we send to the FW
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* @status: The reply from the FW
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*
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* Bit-bangs the cmd to the by_pass FW status points to what is returned.
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**/
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#define IXGBE_BYPASS_BB_WAIT 1
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static s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
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{
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int i;
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u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
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u32 esdp;
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if (!status)
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return IXGBE_ERR_PARAM;
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*status = 0;
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/* SDP vary by MAC type */
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switch (hw->mac.type) {
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case ixgbe_mac_82599EB:
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sck = IXGBE_ESDP_SDP7;
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sdi = IXGBE_ESDP_SDP0;
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sdo = IXGBE_ESDP_SDP6;
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dir_sck = IXGBE_ESDP_SDP7_DIR;
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dir_sdi = IXGBE_ESDP_SDP0_DIR;
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dir_sdo = IXGBE_ESDP_SDP6_DIR;
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break;
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case ixgbe_mac_X540:
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sck = IXGBE_ESDP_SDP2;
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sdi = IXGBE_ESDP_SDP0;
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sdo = IXGBE_ESDP_SDP1;
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dir_sck = IXGBE_ESDP_SDP2_DIR;
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dir_sdi = IXGBE_ESDP_SDP0_DIR;
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dir_sdo = IXGBE_ESDP_SDP1_DIR;
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break;
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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sck = IXGBE_ESDP_SDP2;
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sdi = IXGBE_ESDP_SDP0;
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sdo = IXGBE_ESDP_SDP1;
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dir_sck = IXGBE_ESDP_SDP2_DIR;
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dir_sdi = IXGBE_ESDP_SDP0_DIR;
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dir_sdo = IXGBE_ESDP_SDP1_DIR;
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break;
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default:
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return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
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}
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/* Set SDP pins direction */
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esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
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esdp |= dir_sck; /* SCK as output */
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esdp |= dir_sdi; /* SDI as output */
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esdp &= ~dir_sdo; /* SDO as input */
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esdp |= sck;
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esdp |= sdi;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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// TODO:
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msleep(IXGBE_BYPASS_BB_WAIT);
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/* Generate start condition */
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esdp &= ~sdi;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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msleep(IXGBE_BYPASS_BB_WAIT);
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esdp &= ~sck;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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msleep(IXGBE_BYPASS_BB_WAIT);
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/* Clock out the new control word and clock in the status */
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for (i = 0; i < 32; i++) {
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if ((cmd >> (31 - i)) & 0x01) {
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esdp |= sdi;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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} else {
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esdp &= ~sdi;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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}
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IXGBE_WRITE_FLUSH(hw);
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msleep(IXGBE_BYPASS_BB_WAIT);
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esdp |= sck;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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msleep(IXGBE_BYPASS_BB_WAIT);
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esdp &= ~sck;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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msleep(IXGBE_BYPASS_BB_WAIT);
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esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
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if (esdp & sdo)
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*status = (*status << 1) | 0x01;
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else
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*status = (*status << 1) | 0x00;
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msleep(IXGBE_BYPASS_BB_WAIT);
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}
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/* stop condition */
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esdp |= sck;
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esdp &= ~sdi;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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msleep(IXGBE_BYPASS_BB_WAIT);
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esdp |= sdi;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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IXGBE_WRITE_FLUSH(hw);
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/* set the page bits to match the cmd that the status it belongs to */
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*status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
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return 0;
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}
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/**
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* ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
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*
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* If we send a write we can't be sure it took until we can read back
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* that same register. It can be a problem as some of the feilds may
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* for valid reasons change between the time wrote the register and
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* we read it again to verify. So this function check everything we
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* can check and then assumes it worked.
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*
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* @u32 in_reg - The register cmd for the bit-bang read.
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* @u32 out_reg - The register returned from a bit-bang read.
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**/
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static bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
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{
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u32 mask;
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/* Page must match for all control pages */
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if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
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return false;
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switch (in_reg & BYPASS_PAGE_M) {
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case BYPASS_PAGE_CTL0:
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/* All the following can't change since the last write
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* - All the event actions
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* - The timeout value
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*/
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mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
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BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
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BYPASS_WDTIMEOUT_M |
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BYPASS_WDT_VALUE_M;
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if ((out_reg & mask) != (in_reg & mask))
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return false;
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/* 0x0 is never a valid value for bypass status */
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if (!(out_reg & BYPASS_STATUS_OFF_M))
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return false;
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break;
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case BYPASS_PAGE_CTL1:
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/* All the following can't change since the last write
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* - time valid bit
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* - time we last sent
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*/
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mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
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if ((out_reg & mask) != (in_reg & mask))
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return false;
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break;
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case BYPASS_PAGE_CTL2:
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/* All we can check in this page is control number
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* which is already done above.
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*/
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break;
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}
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/* We are as sure as we can be return true */
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return true;
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}
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/**
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* ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
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*
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* @hw: pointer to hardware structure
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* @cmd: The control word we are setting.
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* @event: The event we are setting in the FW. This also happens to
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* be the mask for the event we are setting (handy)
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* @action: The action we set the event to in the FW. This is in a
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* bit field that happens to be what we want to put in
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* the event spot (also handy)
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**/
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static s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
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u32 action)
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{
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u32 by_ctl = 0;
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u32 cmd, verify;
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u32 count = 0;
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/* Get current values */
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cmd = ctrl; /* just reading only need control number */
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if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
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return IXGBE_ERR_INVALID_ARGUMENT;
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/* Set to new action */
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cmd = (by_ctl & ~event) | BYPASS_WE | action;
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if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
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return IXGBE_ERR_INVALID_ARGUMENT;
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/* Page 0 force a FW eeprom write which is slow so verify */
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if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
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verify = BYPASS_PAGE_CTL0;
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do {
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if (count++ > 5)
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return IXGBE_BYPASS_FW_WRITE_FAILURE;
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if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
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return IXGBE_ERR_INVALID_ARGUMENT;
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} while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
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} else {
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/* We have give the FW time for the write to stick */
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msleep(100);
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}
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return 0;
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}
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/**
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* ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom address.
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*
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* @hw: pointer to hardware structure
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* @addr: The bypass eeprom address to read.
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* @value: The 8b of data at the address above.
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**/
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static s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
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{
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u32 cmd;
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u32 status;
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/* send the request */
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cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
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cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
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if (ixgbe_bypass_rw_generic(hw, cmd, &status))
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return IXGBE_ERR_INVALID_ARGUMENT;
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/* We have give the FW time for the write to stick */
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msleep(100);
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/* now read the results */
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cmd &= ~BYPASS_WE;
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if (ixgbe_bypass_rw_generic(hw, cmd, &status))
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return IXGBE_ERR_INVALID_ARGUMENT;
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*value = status & BYPASS_CTL2_DATA_M;
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return 0;
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}
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#endif /* RTE_NIC_BYPASS */
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#endif /* _IXGBE_BYPASS_API_H_ */
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