0c4546de45
This patch replaces the mixed QAT symmetric and asymmetric support implementation by separate files with shared or individual implementation for specific QAT generation. Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021 Intel Corporation
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*/
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#ifndef _QAT_CRYPTO_H_
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#define _QAT_CRYPTO_H_
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#include <rte_cryptodev.h>
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#include "qat_device.h"
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extern uint8_t qat_sym_driver_id;
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extern uint8_t qat_asym_driver_id;
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/** helper macro to set cryptodev capability range **/
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#define CAP_RNG(n, l, r, i) .n = {.min = l, .max = r, .increment = i}
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#define CAP_RNG_ZERO(n) .n = {.min = 0, .max = 0, .increment = 0}
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/** helper macro to set cryptodev capability value **/
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#define CAP_SET(n, v) .n = v
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/** private data structure for a QAT device.
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* there can be one of these on each qat_pci_device (VF).
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*/
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struct qat_cryptodev_private {
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struct qat_pci_device *qat_dev;
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/**< The qat pci device hosting the service */
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uint8_t dev_id;
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/**< Device instance for this rte_cryptodev */
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const struct rte_cryptodev_capabilities *qat_dev_capabilities;
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/* QAT device symmetric crypto capabilities */
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const struct rte_memzone *capa_mz;
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/* Shared memzone for storing capabilities */
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uint16_t min_enq_burst_threshold;
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uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */
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enum qat_service_type service_type;
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};
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struct qat_capabilities_info {
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struct rte_cryptodev_capabilities *data;
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uint64_t size;
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};
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typedef struct qat_capabilities_info (*get_capabilities_info_t)
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(struct qat_pci_device *qat_dev);
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typedef uint64_t (*get_feature_flags_t)(struct qat_pci_device *qat_dev);
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typedef void * (*create_security_ctx_t)(void *cryptodev);
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struct qat_crypto_gen_dev_ops {
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get_feature_flags_t get_feature_flags;
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get_capabilities_info_t get_capabilities;
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struct rte_cryptodev_ops *cryptodev_ops;
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#ifdef RTE_LIB_SECURITY
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create_security_ctx_t create_security_ctx;
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#endif
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};
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int
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qat_cryptodev_config(struct rte_cryptodev *dev,
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struct rte_cryptodev_config *config);
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int
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qat_cryptodev_start(struct rte_cryptodev *dev);
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void
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qat_cryptodev_stop(struct rte_cryptodev *dev);
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int
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qat_cryptodev_close(struct rte_cryptodev *dev);
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void
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qat_cryptodev_info_get(struct rte_cryptodev *dev,
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struct rte_cryptodev_info *info);
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void
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qat_cryptodev_stats_get(struct rte_cryptodev *dev,
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struct rte_cryptodev_stats *stats);
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void
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qat_cryptodev_stats_reset(struct rte_cryptodev *dev);
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int
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qat_cryptodev_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
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const struct rte_cryptodev_qp_conf *qp_conf, int socket_id);
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int
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qat_cryptodev_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id);
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#endif
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