numam-dpdk/drivers/event/octeontx2
Pavan Nikhilesh aa62547f7e event/octeontx2: add SSO dual workslot mode
OcteonTx2 AP core SSO cache contains two entries each entry caches
state of an single GWS aka event port.
AP core requests events from SSO by using following sequence :
1. Write to SSOW_LF_GWS_OP_GET_WORK
2. Wait for SSO to complete scheduling by polling on SSOW_LF_GWS_TAG[63]
3. SSO notifies core by clearing SSOW_LF_GWS_TAG[63] and if work is
valid SSOW_LF_GWS_WQP is non-zero.
The above sequence uses only one in-core cache entry.

In dual workslot mode we try to use both the in-core cache entries by
triggering GET_WORK on a second workslot as soon as the above sequence
completes. This effectively hides the schedule latency of SSO if there
are enough events with unique flow_tags in-flight.
This mode reserves two SSO GWS lf's for each event port effectively
doubling single core performance.
Dual workslot mode is the default mode of operation in octeontx2.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
2019-07-03 06:56:10 +02:00
..
Makefile event/octeontx2: add SSO HW device operations 2019-07-03 06:56:07 +02:00
meson.build event/octeontx2: add SSO HW device operations 2019-07-03 06:56:07 +02:00
otx2_evdev_irq.c event/octeontx2: add SSO dual workslot mode 2019-07-03 06:56:10 +02:00
otx2_evdev_stats.h event/octeontx2: add SSO dual workslot mode 2019-07-03 06:56:10 +02:00
otx2_evdev.c event/octeontx2: add SSO dual workslot mode 2019-07-03 06:56:10 +02:00
otx2_evdev.h event/octeontx2: add SSO dual workslot mode 2019-07-03 06:56:10 +02:00
otx2_worker.c event/octeontx2: add worker dequeue functions 2019-07-03 06:56:09 +02:00
otx2_worker.h event/octeontx2: add SSO HW device operations 2019-07-03 06:56:07 +02:00
rte_pmd_octeontx2_event_version.map event/octeontx2: add build infra and device probe 2019-07-03 06:55:44 +02:00