fca5acb35e
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Harry van Haaren <harry.van.haaren@intel.com> Acked-by: Keith Wiles <keith.wiles@intel.com> Acked-by: Luca Boccassi <luca.boccassi@gmail.com>
106 lines
3.5 KiB
C
106 lines
3.5 KiB
C
/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Header file containing DPDK compilation parameters
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*
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* Header file containing DPDK compilation parameters. Also include the
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* meson-generated header file containing the detected parameters that
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* are variable across builds or build environments.
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*
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* NOTE: This file is only used for meson+ninja builds. For builds done
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* using make/gmake, the rte_config.h file is autogenerated from the
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* defconfig_* files in the config directory.
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*/
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#ifndef _RTE_CONFIG_H_
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#define _RTE_CONFIG_H_
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#include <rte_build_config.h>
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/****** library defines ********/
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/* EAL defines */
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#define RTE_MAX_MEMSEG 512
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#define RTE_MAX_MEMZONE 2560
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#define RTE_MAX_TAILQ 32
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#define RTE_LOG_LEVEL RTE_LOG_INFO
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#define RTE_LOG_DP_LEVEL RTE_LOG_INFO
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#define RTE_BACKTRACE 1
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#define RTE_EAL_VFIO 1
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/* mempool defines */
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#define RTE_MEMPOOL_CACHE_MAX_SIZE 512
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/* mbuf defines */
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#define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
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#define RTE_MBUF_REFCNT_ATOMIC 1
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#define RTE_PKTMBUF_HEADROOM 128
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/* ether defines */
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#define RTE_MAX_ETHPORTS 32
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#define RTE_MAX_QUEUES_PER_PORT 1024
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#define RTE_ETHDEV_QUEUE_STAT_CNTRS 16
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#define RTE_ETHDEV_RXTX_CALLBACKS 1
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/* cryptodev defines */
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#define RTE_CRYPTO_MAX_DEVS 64
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#define RTE_CRYPTODEV_NAME_LEN 64
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/* eventdev defines */
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#define RTE_EVENT_MAX_DEVS 16
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#define RTE_EVENT_MAX_QUEUES_PER_DEV 64
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/* ip_fragmentation defines */
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#define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
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#undef RTE_LIBRTE_IP_FRAG_TBL_STAT
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/* rte_power defines */
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#define RTE_MAX_LCORE_FREQS 64
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/* rte_sched defines */
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#undef RTE_SCHED_RED
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#undef RTE_SCHED_COLLECT_STATS
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#undef RTE_SCHED_SUBPORT_TC_OV
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#define RTE_SCHED_PORT_N_GRINDERS 8
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#undef RTE_SCHED_VECTOR
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/****** driver defines ********/
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/*
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* Number of sessions to create in the session memory pool
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* on a single QuickAssist device.
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*/
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#define RTE_QAT_PMD_MAX_NB_SESSIONS 2048
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#endif /* _RTE_CONFIG_H_ */
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