numam-dpdk/drivers/net/bnxt/bnxt_txq.h
Sriharsha Basavapatna adcee0fc84 net/bnxt: fix Tx batching
This patch addresses the following issues with Tx batching:

1. Tx stall observed in some conditions:

The batching code doesn't request for a completion when only a partial
chain of packets is transmitted due to mbuf allocation errors. Because
of this, Tx consumer index is not updated correctly and it eventually
leads to qfull condition. Fix this by requesting a completion for the
last packet in the partial chain that is transmitted successfully.

2. Tx stall seen with Jumbo frames:

With jumbo frames, number of TxBDs is > 1. While setting up these
additional BDs in bnxt_start_xmit(), the flags field is being set using
the OR-assignment operator. We end up using a stale value of the flags
field (from a previous use of that descriptor). This results in an
invalid completion and eventually leads to tx stall. Fix this to just
assign the flags field with the right value.

Fixes: 5735eb2419 ("net/bnxt: support Tx batching")
Cc: stable@dpdk.org

Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2019-05-27 18:09:07 +02:00

47 lines
1.5 KiB
C

/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2018 Broadcom
* All rights reserved.
*/
#ifndef _BNXT_TXQ_H_
#define _BNXT_TXQ_H_
struct bnxt_tx_ring_info;
struct bnxt_cp_ring_info;
struct bnxt_tx_queue {
uint16_t nb_tx_desc; /* number of TX descriptors */
uint16_t tx_free_thresh;/* minimum TX before freeing */
/** Index to last TX descriptor to have been cleaned. */
uint16_t last_desc_cleaned;
/** Total number of TX descriptors ready to be allocated. */
uint16_t tx_next_dd; /* next desc to scan for DD bit */
uint16_t tx_next_rs; /* next desc to set RS bit */
uint16_t queue_id; /* TX queue index */
uint16_t reg_idx; /* TX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t pthresh; /* Prefetch threshold register */
uint8_t hthresh; /* Host threshold register */
uint8_t wthresh; /* Write-back threshold reg */
uint32_t ctx_curr; /* Hardware context states */
uint8_t tx_deferred_start; /* not in global dev start */
struct bnxt *bp;
int index;
int tx_wake_thresh;
struct bnxt_tx_ring_info *tx_ring;
unsigned int cp_nr_rings;
struct bnxt_cp_ring_info *cp_ring;
const struct rte_memzone *mz;
};
void bnxt_free_txq_stats(struct bnxt_tx_queue *txq);
void bnxt_free_tx_mbufs(struct bnxt *bp);
void bnxt_tx_queue_release_op(void *tx_queue);
int bnxt_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
uint16_t queue_idx,
uint16_t nb_desc,
unsigned int socket_id,
const struct rte_eth_txconf *tx_conf);
#endif