48f31ca50c
This application is purposefully built to benchmark the performance of the Intel DPDK Packet Framework toolbox. It uses 3 CPU cores connected in a chain through SW rings (NICs --> Core A --> Core B --> Core C --> NICs) 1. Core A: reads packets from NIC ports and writes them to SW queues; 2. Core B: instantiates a Packet Framework pipeline that uses ring reader input ports, a table whose type is selected trhough command line arguments (--none, --stub, --lpm, --acl, --hash[-spec]-KEYSZ-TYPE, with KEYSZ as 8, 16 or 32 bytes and TYPE as ext (Extendible bucket) or lru (LRU)) and ring writers output ports; 3. Core C: reads packets from SW rings and writes them to NIC ports. Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com> Acked-by: Pablo de Lara Guarch <pablo.de.lara.guarch@intel.com> Acked by: Ivan Boule <ivan.boule@6wind.com> [Thomas: remove dedicated build option]
149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MAIN_H_
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#define _MAIN_H_
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#ifndef APP_MBUF_ARRAY_SIZE
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#define APP_MBUF_ARRAY_SIZE 256
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#endif
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struct app_mbuf_array {
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struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
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uint16_t n_mbufs;
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};
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#ifndef APP_MAX_PORTS
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#define APP_MAX_PORTS 4
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#endif
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struct app_params {
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/* CPU cores */
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uint32_t core_rx;
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uint32_t core_worker;
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uint32_t core_tx;
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/* Ports*/
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uint32_t ports[APP_MAX_PORTS];
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uint32_t n_ports;
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uint32_t port_rx_ring_size;
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uint32_t port_tx_ring_size;
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/* Rings */
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struct rte_ring *rings_rx[APP_MAX_PORTS];
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struct rte_ring *rings_tx[APP_MAX_PORTS];
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uint32_t ring_rx_size;
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uint32_t ring_tx_size;
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/* Internal buffers */
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struct app_mbuf_array mbuf_rx;
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struct app_mbuf_array mbuf_tx[APP_MAX_PORTS];
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/* Buffer pool */
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struct rte_mempool *pool;
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uint32_t pool_buffer_size;
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uint32_t pool_size;
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uint32_t pool_cache_size;
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/* Burst sizes */
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uint32_t burst_size_rx_read;
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uint32_t burst_size_rx_write;
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uint32_t burst_size_worker_read;
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uint32_t burst_size_worker_write;
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uint32_t burst_size_tx_read;
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uint32_t burst_size_tx_write;
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/* App behavior */
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uint32_t pipeline_type;
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} __rte_cache_aligned;
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extern struct app_params app;
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int app_parse_args(int argc, char **argv);
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void app_print_usage(void);
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void app_init(void);
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int app_lcore_main_loop(void *arg);
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/* Pipeline */
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enum {
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e_APP_PIPELINE_NONE = 0,
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e_APP_PIPELINE_STUB,
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e_APP_PIPELINE_HASH_KEY8_EXT,
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e_APP_PIPELINE_HASH_KEY8_LRU,
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e_APP_PIPELINE_HASH_KEY16_EXT,
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e_APP_PIPELINE_HASH_KEY16_LRU,
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e_APP_PIPELINE_HASH_KEY32_EXT,
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e_APP_PIPELINE_HASH_KEY32_LRU,
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e_APP_PIPELINE_HASH_SPEC_KEY8_EXT,
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e_APP_PIPELINE_HASH_SPEC_KEY8_LRU,
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e_APP_PIPELINE_HASH_SPEC_KEY16_EXT,
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e_APP_PIPELINE_HASH_SPEC_KEY16_LRU,
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e_APP_PIPELINE_HASH_SPEC_KEY32_EXT,
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e_APP_PIPELINE_HASH_SPEC_KEY32_LRU,
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e_APP_PIPELINE_ACL,
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e_APP_PIPELINE_LPM,
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e_APP_PIPELINE_LPM_IPV6,
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e_APP_PIPELINES
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};
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void app_main_loop_rx(void);
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void app_main_loop_rx_metadata(void);
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uint64_t test_hash(void *key, uint32_t key_size, uint64_t seed);
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void app_main_loop_worker(void);
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void app_main_loop_worker_pipeline_stub(void);
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void app_main_loop_worker_pipeline_hash(void);
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void app_main_loop_worker_pipeline_acl(void);
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void app_main_loop_worker_pipeline_lpm(void);
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void app_main_loop_worker_pipeline_lpm_ipv6(void);
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void app_main_loop_tx(void);
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#define APP_FLUSH 0
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#ifndef APP_FLUSH
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#define APP_FLUSH 0x3FF
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#endif
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#ifdef RTE_EXEC_ENV_BAREMETAL
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#define MAIN _main
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#else
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#define MAIN main
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#endif
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int MAIN(int argc, char **argv);
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#endif /* _MAIN_H_ */
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