5630257fcc
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
148 lines
6.3 KiB
ReStructuredText
148 lines
6.3 KiB
ReStructuredText
.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2010-2014 Intel Corporation.
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.. _Mempool_Library:
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Mempool Library
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===============
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A memory pool is an allocator of a fixed-sized object.
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In the DPDK, it is identified by name and uses a mempool handler to store free objects.
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The default mempool handler is ring based.
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It provides some other optional services such as a per-core object cache and
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an alignment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.
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This library is used by the :ref:`Mbuf Library <Mbuf_Library>`.
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Cookies
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-------
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In debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled), cookies are added at the beginning and end of allocated blocks.
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The allocated objects then contain overwrite protection fields to help debugging buffer overflows.
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Stats
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-----
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In debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),
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statistics about get from/put in the pool are stored in the mempool structure.
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Statistics are per-lcore to avoid concurrent access to statistics counters.
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Memory Alignment Constraints
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----------------------------
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Depending on hardware memory configuration, performance can be greatly improved by adding a specific padding between objects.
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The objective is to ensure that the beginning of each object starts on a different channel and rank in memory so that all channels are equally loaded.
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This is particularly true for packet buffers when doing L3 forwarding or flow classification.
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Only the first 64 bytes are accessed, so performance can be increased by spreading the start addresses of objects among the different channels.
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The number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM.
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The ranks cannot be accessed simultaneously since they share the same data path.
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The physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks.
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When running an application, the EAL command line options provide the ability to add the number of memory channels and ranks.
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.. note::
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The command line must always have the number of memory channels specified for the processor.
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Examples of alignment for different DIMM architectures are shown in
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:numref:`figure_memory-management` and :numref:`figure_memory-management2`.
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.. _figure_memory-management:
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.. figure:: img/memory-management.*
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Two Channels and Quad-ranked DIMM Example
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In this case, the assumption is that a packet is 16 blocks of 64 bytes, which is not true.
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The Intel® 5520 chipset has three channels, so in most cases,
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no padding is required between objects (except for objects whose size are n x 3 x 64 bytes blocks).
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.. _figure_memory-management2:
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.. figure:: img/memory-management2.*
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Three Channels and Two Dual-ranked DIMM Example
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When creating a new pool, the user can specify to use this feature or not.
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.. _mempool_local_cache:
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Local Cache
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-----------
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In terms of CPU usage, the cost of multiple cores accessing a memory pool's ring of free buffers may be high
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since each access requires a compare-and-set (CAS) operation.
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To avoid having too many access requests to the memory pool's ring,
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the memory pool allocator can maintain a per-core cache and do bulk requests to the memory pool's ring,
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via the cache with many fewer locks on the actual memory pool structure.
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In this way, each core has full access to its own cache (with locks) of free objects and
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only when the cache fills does the core need to shuffle some of the free objects back to the pools ring or
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obtain more objects when the cache is empty.
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While this may mean a number of buffers may sit idle on some core's cache,
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the speed at which a core can access its own cache for a specific memory pool without locks provides performance gains.
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The cache is composed of a small, per-core table of pointers and its length (used as a stack).
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This internal cache can be enabled or disabled at creation of the pool.
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The maximum size of the cache is static and is defined at compilation time (CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE).
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:numref:`figure_mempool` shows a cache in operation.
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.. _figure_mempool:
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.. figure:: img/mempool.*
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A mempool in Memory with its Associated Ring
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Alternatively to the internal default per-lcore local cache, an application can create and manage external caches through the ``rte_mempool_cache_create()``, ``rte_mempool_cache_free()`` and ``rte_mempool_cache_flush()`` calls.
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These user-owned caches can be explicitly passed to ``rte_mempool_generic_put()`` and ``rte_mempool_generic_get()``.
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The ``rte_mempool_default_cache()`` call returns the default internal cache if any.
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In contrast to the default caches, user-owned caches can be used by non-EAL threads too.
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Mempool Handlers
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------------------------
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This allows external memory subsystems, such as external hardware memory
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management systems and software based memory allocators, to be used with DPDK.
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There are two aspects to a mempool handler.
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* Adding the code for your new mempool operations (ops). This is achieved by
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adding a new mempool ops code, and using the ``MEMPOOL_REGISTER_OPS`` macro.
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* Using the new API to call ``rte_mempool_create_empty()`` and
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``rte_mempool_set_ops_byname()`` to create a new mempool and specifying which
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ops to use.
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Several different mempool handlers may be used in the same application. A new
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mempool can be created by using the ``rte_mempool_create_empty()`` function,
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then using ``rte_mempool_set_ops_byname()`` to point the mempool to the
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relevant mempool handler callback (ops) structure.
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Legacy applications may continue to use the old ``rte_mempool_create()`` API
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call, which uses a ring based mempool handler by default. These applications
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will need to be modified to use a new mempool handler.
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For applications that use ``rte_pktmbuf_create()``, there is a config setting
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(``RTE_MBUF_DEFAULT_MEMPOOL_OPS``) that allows the application to make use of
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an alternative mempool handler.
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Use Cases
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---------
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All allocations that require a high level of performance should use a pool-based memory allocator.
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Below are some examples:
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* :ref:`Mbuf Library <Mbuf_Library>`
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* :ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` , for logging service
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* Any application that needs to allocate fixed-sized objects in the data plane and that will be continuously utilized by the system.
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