0f20acbf5e
MPRQ (Multi-Packet Rx Queue) processes one packet at a time using simple scalar instructions. MPRQ works by posting a single large buffer (consisted of multiple fixed-size strides) in order to receive multiple packets at once on this buffer. A Rx packet is then copied to a user-provided mbuf or PMD attaches the Rx packet to the mbuf by the pointer to an external buffer. There is an opportunity to speed up the packet receiving by processing 4 packets simultaneously using SIMD (single instruction, multiple data) extensions. Allocate mbufs in batches for every MPRQ buffer and process the packets in groups of 4 until all the strides are exhausted. Then switch to another MPRQ buffer and repeat the process over again. The vectorized MPRQ burst routine is engaged automatically in case the mprq_en=1 devarg is specified and the vectorization is not disabled explicitly by providing rx_vec_en=0 devarg. There is a limitation: LRO is not supported and scalar MPRQ is selected if it is on. Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
71 lines
2.5 KiB
C
71 lines
2.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2017 6WIND S.A.
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* Copyright 2017 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_RXTX_VEC_H_
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#define RTE_PMD_MLX5_RXTX_VEC_H_
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#include <rte_common.h>
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#include <rte_mbuf.h>
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#include <mlx5_prm.h>
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#include "mlx5_autoconf.h"
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#include "mlx5_mr.h"
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/* HW checksum offload capabilities of vectorized Tx. */
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#define MLX5_VEC_TX_CKSUM_OFFLOAD_CAP \
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(DEV_TX_OFFLOAD_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
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/*
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* Compile time sanity check for vectorized functions.
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*/
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#define S_ASSERT_RTE_MBUF(s) \
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static_assert(s, "A field of struct rte_mbuf is changed")
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#define S_ASSERT_MLX5_CQE(s) \
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static_assert(s, "A field of struct mlx5_cqe is changed")
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/* rxq_cq_decompress_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, hash) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
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/* rxq_cq_to_ptype_oflags_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, ol_flags) ==
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offsetof(struct rte_mbuf, rearm_data) + 8);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, rearm_data) ==
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RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
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/* rxq_burst_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
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#if (RTE_CACHE_LINE_SIZE == 128)
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 64);
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#else
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 0);
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#endif
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rx_hash_res) ==
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offsetof(struct mlx5_cqe, pkt_info) + 12);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rsvd1) + 11 ==
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offsetof(struct mlx5_cqe, hdr_type_etc));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, vlan_info) ==
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offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, lro_num_seg) + 12 ==
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offsetof(struct mlx5_cqe, byte_cnt));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, sop_drop_qpn) ==
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RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, op_own) ==
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offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
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#endif /* RTE_PMD_MLX5_RXTX_VEC_H_ */
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