b2fe569359
In SF bug 61297 it's been confirmed that the hardware does not always calculate the TCP checksum correctly with TSO sends. The value of the Total Length field (IPv4) or Payload Length field (IPv6) is the critical factor. We're sufficiently confident that if these fields are zero then the checksum will be calculated correctly. The information may be used by the drivers to check if the workaround is required when FATSOv2 is implemented. Signed-off-by: Mark Spender <mspender@solarflare.com> Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
236 lines
6.5 KiB
C
236 lines
6.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2012-2018 Solarflare Communications Inc.
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* All rights reserved.
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*/
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_MON_MCDI
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#include "mcdi_mon.h"
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#endif
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#if EFSYS_OPT_HUNTINGTON
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#include "ef10_tlv_layout.h"
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static __checkReturn efx_rc_t
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hunt_nic_get_required_pcie_bandwidth(
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__in efx_nic_t *enp,
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__out uint32_t *bandwidth_mbpsp)
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{
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uint32_t port_modes;
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uint32_t max_port_mode;
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uint32_t bandwidth;
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efx_rc_t rc;
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/*
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* On Huntington, the firmware may not give us the current port mode, so
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* we need to go by the set of available port modes and assume the most
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* capable mode is in use.
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*/
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if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
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NULL, NULL)) != 0) {
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/* No port mode info available */
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bandwidth = 0;
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goto out;
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}
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if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
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/*
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* This needs the full PCIe bandwidth (and could use
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* more) - roughly 64 Gbit/s for 8 lanes of Gen3.
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*/
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if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
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EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
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goto fail1;
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} else {
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if (port_modes & (1U << TLV_PORT_MODE_40G)) {
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max_port_mode = TLV_PORT_MODE_40G;
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} else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
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max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
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} else {
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/* Assume two 10G ports */
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max_port_mode = TLV_PORT_MODE_10G_10G;
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}
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if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
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&bandwidth)) != 0)
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goto fail2;
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}
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out:
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*bandwidth_mbpsp = bandwidth;
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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hunt_board_cfg(
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__in efx_nic_t *enp)
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{
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_port_t *epp = &(enp->en_port);
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uint32_t flags;
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uint32_t sysclk, dpcpu_clk;
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uint32_t bandwidth;
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efx_rc_t rc;
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/*
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* Enable firmware workarounds for hardware errata.
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* Expected responses are:
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* - 0 (zero):
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* Success: workaround enabled or disabled as requested.
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* - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
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* Firmware does not support the MC_CMD_WORKAROUND request.
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* (assume that the workaround is not supported).
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* - MC_CMD_ERR_ENOENT (reported as ENOENT):
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* Firmware does not support the requested workaround.
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* - MC_CMD_ERR_EPERM (reported as EACCES):
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* Unprivileged function cannot enable/disable workarounds.
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*
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* See efx_mcdi_request_errcode() for MCDI error translations.
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*/
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/*
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* If the bug35388 workaround is enabled, then use an indirect access
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* method to avoid unsafe EVQ writes.
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*/
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rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
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NULL);
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if ((rc == 0) || (rc == EACCES))
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encp->enc_bug35388_workaround = B_TRUE;
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else if ((rc == ENOTSUP) || (rc == ENOENT))
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encp->enc_bug35388_workaround = B_FALSE;
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else
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goto fail1;
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/*
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* If the bug41750 workaround is enabled, then do not test interrupts,
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* as the test will fail (seen with Greenport controllers).
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*/
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rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
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NULL);
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if (rc == 0) {
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encp->enc_bug41750_workaround = B_TRUE;
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} else if (rc == EACCES) {
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/* Assume a controller with 40G ports needs the workaround. */
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if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
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encp->enc_bug41750_workaround = B_TRUE;
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else
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encp->enc_bug41750_workaround = B_FALSE;
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} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
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encp->enc_bug41750_workaround = B_FALSE;
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} else {
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goto fail2;
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}
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if (EFX_PCI_FUNCTION_IS_VF(encp)) {
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/* Interrupt testing does not work for VFs. See bug50084. */
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encp->enc_bug41750_workaround = B_TRUE;
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}
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/*
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* If the bug26807 workaround is enabled, then firmware has enabled
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* support for chained multicast filters. Firmware will reset (FLR)
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* functions which have filters in the hardware filter table when the
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* workaround is enabled/disabled.
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*
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* We must recheck if the workaround is enabled after inserting the
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* first hardware filter, in case it has been changed since this check.
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*/
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rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
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B_TRUE, &flags);
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if (rc == 0) {
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encp->enc_bug26807_workaround = B_TRUE;
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if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
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/*
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* Other functions had installed filters before the
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* workaround was enabled, and they have been reset
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* by firmware.
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*/
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EFSYS_PROBE(bug26807_workaround_flr_done);
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/* FIXME: bump MC warm boot count ? */
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}
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} else if (rc == EACCES) {
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/*
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* Unprivileged functions cannot enable the workaround in older
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* firmware.
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*/
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encp->enc_bug26807_workaround = B_FALSE;
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} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
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encp->enc_bug26807_workaround = B_FALSE;
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} else {
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goto fail3;
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}
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/* Get clock frequencies (in MHz). */
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if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
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goto fail4;
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/*
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* The Huntington timer quantum is 1536 sysclk cycles, documented for
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* the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
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*/
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encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
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if (encp->enc_bug35388_workaround) {
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encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
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ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
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} else {
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encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
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FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
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}
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encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
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/* Checksums for TSO sends can be incorrect on Huntington. */
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encp->enc_bug61297_workaround = B_TRUE;
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/* Alignment for receive packet DMA buffers */
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encp->enc_rx_buf_align_start = 1;
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encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
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/*
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* The workaround for bug35388 uses the top bit of transmit queue
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* descriptor writes, preventing the use of 4096 descriptor TXQs.
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*/
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encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
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EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
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encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
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encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
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encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
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if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
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goto fail5;
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encp->enc_required_pcie_bandwidth_mbps = bandwidth;
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/* All Huntington devices have a PCIe Gen3, 8 lane connector */
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encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
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return (0);
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fail5:
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EFSYS_PROBE(fail5);
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fail4:
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EFSYS_PROBE(fail4);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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#endif /* EFSYS_OPT_HUNTINGTON */
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