0899a87ce7
Arm port of ipsec_mb library [1] has different header file name than the Intel ipsec_mb library. Proper header name is picked according to the architecture to get the code compile when ipsec_mb is installed on Arm platform. And the Arm port currently supports ZUC and SNOW3g. Call to other algorithms will be blocked. [1] https://gitlab.arm.com/arm-reference-solutions/ipsec-mb/-/tree/main Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Ashwin Sekhar T K <asekhar@marvell.com>
192 lines
4.7 KiB
C
192 lines
4.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021 Intel Corporation
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*/
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#include <bus_vdev_driver.h>
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#include <rte_common.h>
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#include <rte_cryptodev.h>
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#include "ipsec_mb_private.h"
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RTE_DEFINE_PER_LCORE(IMB_MGR *, mb_mgr);
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struct ipsec_mb_internals ipsec_mb_pmds[IPSEC_MB_N_PMD_TYPES];
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int ipsec_mb_logtype_driver;
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enum ipsec_mb_vector_mode vector_mode;
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/**
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* Generic burst enqueue, place crypto operations on ingress queue for
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* processing.
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*
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* @param __qp Queue Pair to process
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* @param ops Crypto operations for processing
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* @param nb_ops Number of crypto operations for processing
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*
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* @return
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* - Number of crypto operations enqueued
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*/
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static uint16_t
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ipsec_mb_enqueue_burst(void *__qp, struct rte_crypto_op **ops,
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uint16_t nb_ops)
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{
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struct ipsec_mb_qp *qp = __qp;
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unsigned int nb_enqueued;
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nb_enqueued = rte_ring_enqueue_burst(qp->ingress_queue,
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(void **)ops, nb_ops, NULL);
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qp->stats.enqueued_count += nb_enqueued;
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qp->stats.enqueue_err_count += nb_ops - nb_enqueued;
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return nb_enqueued;
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}
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int
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ipsec_mb_create(struct rte_vdev_device *vdev,
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enum ipsec_mb_pmd_types pmd_type)
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{
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struct rte_cryptodev *dev;
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struct ipsec_mb_dev_private *internals;
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struct ipsec_mb_internals *pmd_data = &ipsec_mb_pmds[pmd_type];
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struct rte_cryptodev_pmd_init_params init_params = {};
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const char *name, *args;
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int retval;
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#if defined(RTE_ARCH_ARM)
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if ((pmd_type != IPSEC_MB_PMD_TYPE_SNOW3G) &&
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(pmd_type != IPSEC_MB_PMD_TYPE_ZUC))
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return -ENOTSUP;
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#endif
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#if defined(RTE_ARCH_ARM64)
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vector_mode = IPSEC_MB_ARM64;
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#elif defined(RTE_ARCH_X86_64)
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if (vector_mode == IPSEC_MB_NOT_SUPPORTED) {
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/* Check CPU for supported vector instruction set */
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if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
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vector_mode = IPSEC_MB_AVX512;
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else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
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vector_mode = IPSEC_MB_AVX2;
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else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
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vector_mode = IPSEC_MB_AVX;
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else
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vector_mode = IPSEC_MB_SSE;
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}
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#else
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/* Unsupported architecture */
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return -ENOTSUP;
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#endif
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init_params.private_data_size = sizeof(struct ipsec_mb_dev_private) +
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pmd_data->internals_priv_size;
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init_params.max_nb_queue_pairs =
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RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS;
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init_params.socket_id = rte_socket_id();
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name = rte_vdev_device_name(vdev);
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if (name == NULL)
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return -EINVAL;
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args = rte_vdev_device_args(vdev);
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retval = rte_cryptodev_pmd_parse_input_args(&init_params, args);
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if (retval) {
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IPSEC_MB_LOG(
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ERR, "Failed to parse initialisation arguments[%s]", args);
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return -EINVAL;
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}
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dev = rte_cryptodev_pmd_create(name, &vdev->device, &init_params);
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if (dev == NULL) {
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IPSEC_MB_LOG(ERR, "driver %s: create failed",
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init_params.name);
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return -ENODEV;
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}
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/* Set vector instructions mode supported */
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internals = dev->data->dev_private;
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internals->pmd_type = pmd_type;
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internals->max_nb_queue_pairs = init_params.max_nb_queue_pairs;
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dev->driver_id = ipsec_mb_get_driver_id(pmd_type);
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if (dev->driver_id == UINT8_MAX) {
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IPSEC_MB_LOG(ERR, "driver %s: create failed",
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init_params.name);
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return -ENODEV;
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}
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dev->dev_ops = ipsec_mb_pmds[pmd_type].ops;
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dev->enqueue_burst = ipsec_mb_enqueue_burst;
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dev->dequeue_burst = ipsec_mb_pmds[pmd_type].dequeue_burst;
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dev->feature_flags = pmd_data->feature_flags;
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if (pmd_data->dev_config) {
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retval = (*pmd_data->dev_config)(dev);
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if (retval < 0) {
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IPSEC_MB_LOG(ERR,
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"Failed to configure device %s", name);
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rte_cryptodev_pmd_destroy(dev);
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return retval;
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}
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}
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switch (vector_mode) {
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case IPSEC_MB_AVX512:
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dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX512;
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break;
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case IPSEC_MB_AVX2:
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dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2;
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break;
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case IPSEC_MB_AVX:
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dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX;
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break;
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case IPSEC_MB_SSE:
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dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_SSE;
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break;
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default:
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break;
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}
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rte_cryptodev_pmd_probing_finish(dev);
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IPSEC_MB_LOG(INFO, "IPSec Multi-buffer library version used: %s\n",
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imb_get_version_str());
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return 0;
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}
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int
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ipsec_mb_remove(struct rte_vdev_device *vdev)
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{
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struct rte_cryptodev *cryptodev;
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const char *name;
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int qp_id;
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name = rte_vdev_device_name(vdev);
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if (name == NULL)
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return -EINVAL;
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cryptodev = rte_cryptodev_pmd_get_named_dev(name);
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if (cryptodev == NULL)
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return -ENODEV;
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if (RTE_PER_LCORE(mb_mgr)) {
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free_mb_mgr(RTE_PER_LCORE(mb_mgr));
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RTE_PER_LCORE(mb_mgr) = NULL;
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}
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if (cryptodev->security_ctx) {
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rte_free(cryptodev->security_ctx);
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cryptodev->security_ctx = NULL;
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}
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#ifdef AESNI_MB_DOCSIS_SEC_ENABLED
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rte_free(cryptodev->security_ctx);
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cryptodev->security_ctx = NULL;
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#endif
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for (qp_id = 0; qp_id < cryptodev->data->nb_queue_pairs; qp_id++)
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ipsec_mb_qp_release(cryptodev, qp_id);
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return rte_cryptodev_pmd_destroy(cryptodev);
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}
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