334 lines
12 KiB
C
334 lines
12 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of 6WIND S.A. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef RTE_PMD_MLX5_RXTX_H_
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#define RTE_PMD_MLX5_RXTX_H_
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#include <stddef.h>
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#include <stdint.h>
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#include <infiniband/mlx5_hw.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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/* DPDK headers don't like -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include <rte_common.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include "mlx5_utils.h"
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#include "mlx5.h"
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#include "mlx5_autoconf.h"
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#include "mlx5_defs.h"
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#include "mlx5_prm.h"
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struct mlx5_rxq_stats {
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unsigned int idx; /**< Mapping index. */
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#ifdef MLX5_PMD_SOFT_COUNTERS
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uint64_t ipackets; /**< Total of successfully received packets. */
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uint64_t ibytes; /**< Total of successfully received bytes. */
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#endif
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uint64_t idropped; /**< Total of packets dropped when RX ring full. */
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uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
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};
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struct mlx5_txq_stats {
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unsigned int idx; /**< Mapping index. */
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#ifdef MLX5_PMD_SOFT_COUNTERS
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uint64_t opackets; /**< Total of successfully sent packets. */
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uint64_t obytes; /**< Total of successfully sent bytes. */
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#endif
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uint64_t odropped; /**< Total of packets not sent when TX ring full. */
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};
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/* Flow director queue structure. */
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struct fdir_queue {
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struct ibv_qp *qp; /* Associated RX QP. */
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struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
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struct ibv_exp_wq *wq; /* Work queue. */
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struct ibv_cq *cq; /* Completion queue. */
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};
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struct priv;
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/* Compressed CQE context. */
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struct rxq_zip {
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uint16_t ai; /* Array index. */
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uint16_t ca; /* Current array index. */
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uint16_t na; /* Next array index. */
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uint16_t cq_ci; /* The next CQE. */
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uint32_t cqe_cnt; /* Number of CQEs. */
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};
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/* RX queue descriptor. */
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struct rxq {
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unsigned int csum:1; /* Enable checksum offloading. */
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unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
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unsigned int vlan_strip:1; /* Enable VLAN stripping. */
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unsigned int crc_present:1; /* CRC must be subtracted. */
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unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
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unsigned int cqe_n:4; /* Log 2 of CQ elements. */
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unsigned int elts_n:4; /* Log 2 of Mbufs. */
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unsigned int port_id:8;
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unsigned int rss_hash:1; /* RSS hash result is enabled. */
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unsigned int :9; /* Remaining bits. */
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volatile uint32_t *rq_db;
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volatile uint32_t *cq_db;
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uint16_t rq_ci;
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uint16_t cq_ci;
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volatile struct mlx5_wqe_data_seg(*wqes)[];
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volatile struct mlx5_cqe(*cqes)[];
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struct rxq_zip zip; /* Compressed context. */
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struct rte_mbuf *(*elts)[];
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struct rte_mempool *mp;
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struct mlx5_rxq_stats stats;
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} __rte_cache_aligned;
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/* RX queue control descriptor. */
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struct rxq_ctrl {
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struct priv *priv; /* Back pointer to private data. */
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struct ibv_cq *cq; /* Completion Queue. */
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struct ibv_exp_wq *wq; /* Work Queue. */
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struct ibv_exp_res_domain *rd; /* Resource Domain. */
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struct fdir_queue *fdir_queue; /* Flow director queue. */
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struct ibv_mr *mr; /* Memory Region (for mp). */
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struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
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struct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */
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unsigned int socket; /* CPU socket ID for allocations. */
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struct rxq rxq; /* Data path structure. */
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};
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/* Hash RX queue types. */
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enum hash_rxq_type {
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HASH_RXQ_TCPV4,
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HASH_RXQ_UDPV4,
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HASH_RXQ_IPV4,
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HASH_RXQ_TCPV6,
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HASH_RXQ_UDPV6,
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HASH_RXQ_IPV6,
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HASH_RXQ_ETH,
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};
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/* Flow structure with Ethernet specification. It is packed to prevent padding
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* between attr and spec as this layout is expected by libibverbs. */
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struct flow_attr_spec_eth {
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struct ibv_exp_flow_attr attr;
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struct ibv_exp_flow_spec_eth spec;
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} __attribute__((packed));
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/* Define a struct flow_attr_spec_eth object as an array of at least
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* "size" bytes. Room after the first index is normally used to store
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* extra flow specifications. */
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#define FLOW_ATTR_SPEC_ETH(name, size) \
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struct flow_attr_spec_eth name \
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[((size) / sizeof(struct flow_attr_spec_eth)) + \
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!!((size) % sizeof(struct flow_attr_spec_eth))]
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/* Initialization data for hash RX queue. */
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struct hash_rxq_init {
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uint64_t hash_fields; /* Fields that participate in the hash. */
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uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
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unsigned int flow_priority; /* Flow priority to use. */
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union {
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struct {
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enum ibv_exp_flow_spec_type type;
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uint16_t size;
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} hdr;
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struct ibv_exp_flow_spec_tcp_udp tcp_udp;
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struct ibv_exp_flow_spec_ipv4 ipv4;
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struct ibv_exp_flow_spec_ipv6 ipv6;
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struct ibv_exp_flow_spec_eth eth;
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} flow_spec; /* Flow specification template. */
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const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
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};
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/* Initialization data for indirection table. */
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struct ind_table_init {
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unsigned int max_size; /* Maximum number of WQs. */
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/* Hash RX queues using this table. */
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unsigned int hash_types;
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unsigned int hash_types_n;
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};
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/* Initialization data for special flows. */
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struct special_flow_init {
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uint8_t dst_mac_val[6];
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uint8_t dst_mac_mask[6];
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unsigned int hash_types;
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unsigned int per_vlan:1;
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};
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enum hash_rxq_flow_type {
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HASH_RXQ_FLOW_TYPE_PROMISC,
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HASH_RXQ_FLOW_TYPE_ALLMULTI,
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HASH_RXQ_FLOW_TYPE_BROADCAST,
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HASH_RXQ_FLOW_TYPE_IPV6MULTI,
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HASH_RXQ_FLOW_TYPE_MAC,
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};
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#ifndef NDEBUG
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static inline const char *
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hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
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{
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switch (flow_type) {
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case HASH_RXQ_FLOW_TYPE_PROMISC:
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return "promiscuous";
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case HASH_RXQ_FLOW_TYPE_ALLMULTI:
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return "allmulticast";
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case HASH_RXQ_FLOW_TYPE_BROADCAST:
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return "broadcast";
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case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
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return "IPv6 multicast";
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case HASH_RXQ_FLOW_TYPE_MAC:
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return "MAC";
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}
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return NULL;
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}
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#endif /* NDEBUG */
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struct hash_rxq {
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struct priv *priv; /* Back pointer to private data. */
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struct ibv_qp *qp; /* Hash RX QP. */
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enum hash_rxq_type type; /* Hash RX queue type. */
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/* MAC flow steering rules, one per VLAN ID. */
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struct ibv_exp_flow *mac_flow
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[MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
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struct ibv_exp_flow *special_flow
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[MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
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};
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/* TX queue descriptor. */
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RTE_STD_C11
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struct txq {
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uint16_t elts_head; /* Current index in (*elts)[]. */
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uint16_t elts_tail; /* First element awaiting completion. */
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uint16_t elts_comp; /* Counter since last completion request. */
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uint16_t cq_ci; /* Consumer index for completion queue. */
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uint16_t wqe_ci; /* Consumer index for work queue. */
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uint16_t elts_n:4; /* (*elts)[] length (in log2). */
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uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
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uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
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uint16_t bf_buf_size:4; /* Log2 Blueflame size. */
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uint16_t bf_offset; /* Blueflame offset. */
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uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
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uint32_t qp_num_8s; /* QP number shifted by 8. */
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volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
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volatile struct mlx5_wqe64 (*wqes)[]; /* Work queue. */
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volatile uint32_t *qp_db; /* Work queue doorbell. */
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volatile uint32_t *cq_db; /* Completion queue doorbell. */
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volatile void *bf_reg; /* Blueflame register. */
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struct {
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const struct rte_mempool *mp; /* Cached Memory Pool. */
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struct ibv_mr *mr; /* Memory Region (for mp). */
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uint32_t lkey; /* htonl(mr->lkey) */
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} mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
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struct rte_mbuf *(*elts)[]; /* TX elements. */
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struct mlx5_txq_stats stats; /* TX queue counters. */
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} __rte_cache_aligned;
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/* TX queue control descriptor. */
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struct txq_ctrl {
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struct priv *priv; /* Back pointer to private data. */
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struct ibv_cq *cq; /* Completion Queue. */
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struct ibv_qp *qp; /* Queue Pair. */
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struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
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struct ibv_exp_cq_family *if_cq; /* CQ interface. */
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struct ibv_exp_res_domain *rd; /* Resource Domain. */
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unsigned int socket; /* CPU socket ID for allocations. */
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struct txq txq; /* Data path structure. */
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};
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/* mlx5_rxq.c */
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extern const struct hash_rxq_init hash_rxq_init[];
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extern const unsigned int hash_rxq_init_n;
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extern uint8_t rss_hash_default_key[];
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extern const size_t rss_hash_default_key_len;
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size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
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size_t, enum hash_rxq_type);
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int priv_create_hash_rxqs(struct priv *);
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void priv_destroy_hash_rxqs(struct priv *);
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int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
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int priv_rehash_flows(struct priv *);
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void rxq_cleanup(struct rxq_ctrl *);
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int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
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int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
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unsigned int, const struct rte_eth_rxconf *,
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struct rte_mempool *);
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int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
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const struct rte_eth_rxconf *, struct rte_mempool *);
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void mlx5_rx_queue_release(void *);
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uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
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/* mlx5_txq.c */
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void txq_cleanup(struct txq_ctrl *);
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int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
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unsigned int, const struct rte_eth_txconf *);
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int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
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const struct rte_eth_txconf *);
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void mlx5_tx_queue_release(void *);
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uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
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/* mlx5_rxtx.c */
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uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
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uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
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uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
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/* mlx5_mr.c */
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struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
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void txq_mp2mr_iter(struct rte_mempool *, void *);
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uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
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#endif /* RTE_PMD_MLX5_RXTX_H_ */
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