b68d92b45c
Volatilize all Rx/Tx HW negotiation memories to be sure no compiler optimization prevents either load or store commands. Fixes:c3c977bbec("net/mlx4: add Tx bypassing Verbs") Fixes:9f57340a80("net/mlx4: restore Rx offloads") Fixes:6681b84503("net/mlx4: add Rx bypassing Verbs") Fixes:62e96ffb93("net/mlx4: fix no Rx interrupts") Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
162 lines
5.3 KiB
C
162 lines
5.3 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright 2017 6WIND S.A.
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* Copyright 2017 Mellanox
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of 6WIND S.A. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MLX4_PRM_H_
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#define MLX4_PRM_H_
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#include <rte_atomic.h>
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#include <rte_branch_prediction.h>
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#include <rte_byteorder.h>
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/* Verbs headers do not support -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/mlx4dv.h>
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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/* ConnectX-3 Tx queue basic block. */
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#define MLX4_TXBB_SHIFT 6
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#define MLX4_TXBB_SIZE (1 << MLX4_TXBB_SHIFT)
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/* Typical TSO descriptor with 16 gather entries is 352 bytes. */
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#define MLX4_MAX_WQE_SIZE 512
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#define MLX4_MAX_WQE_TXBBS (MLX4_MAX_WQE_SIZE / MLX4_TXBB_SIZE)
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/* Send queue stamping/invalidating information. */
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#define MLX4_SQ_STAMP_STRIDE 64
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#define MLX4_SQ_STAMP_DWORDS (MLX4_SQ_STAMP_STRIDE / 4)
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#define MLX4_SQ_STAMP_SHIFT 31
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#define MLX4_SQ_STAMP_VAL 0x7fffffff
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/* Work queue element (WQE) flags. */
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#define MLX4_BIT_WQE_OWN 0x80000000
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#define MLX4_WQE_CTRL_IIP_HDR_CSUM (1 << 28)
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#define MLX4_WQE_CTRL_IL4_HDR_CSUM (1 << 27)
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#define MLX4_SIZE_TO_TXBBS(size) \
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(RTE_ALIGN((size), (MLX4_TXBB_SIZE)) >> (MLX4_TXBB_SHIFT))
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/* CQE checksum flags. */
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enum {
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MLX4_CQE_L2_TUNNEL_IPV4 = (int)(1u << 25),
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MLX4_CQE_L2_TUNNEL_L4_CSUM = (int)(1u << 26),
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MLX4_CQE_L2_TUNNEL = (int)(1u << 27),
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MLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31),
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};
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/* Send queue information. */
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struct mlx4_sq {
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volatile uint8_t *buf; /**< SQ buffer. */
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volatile uint8_t *eob; /**< End of SQ buffer */
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uint32_t head; /**< SQ head counter in units of TXBBS. */
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uint32_t tail; /**< SQ tail counter in units of TXBBS. */
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uint32_t txbb_cnt; /**< Num of WQEBB in the Q (should be ^2). */
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uint32_t txbb_cnt_mask; /**< txbbs_cnt mask (txbb_cnt is ^2). */
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uint32_t headroom_txbbs; /**< Num of txbbs that should be kept free. */
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volatile uint32_t *db; /**< Pointer to the doorbell. */
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uint32_t doorbell_qpn; /**< qp number to write to the doorbell. */
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};
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#define mlx4_get_send_wqe(sq, n) ((sq)->buf + ((n) * (MLX4_TXBB_SIZE)))
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/* Completion queue events, numbers and masks. */
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#define MLX4_CQ_DB_GEQ_N_MASK 0x3
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#define MLX4_CQ_DOORBELL 0x20
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#define MLX4_CQ_DB_CI_MASK 0xffffff
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/* Completion queue information. */
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struct mlx4_cq {
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volatile void *cq_uar; /**< CQ user access region. */
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volatile void *cq_db_reg; /**< CQ doorbell register. */
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volatile uint32_t *set_ci_db; /**< Pointer to the CQ doorbell. */
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volatile uint32_t *arm_db; /**< Arming Rx events doorbell. */
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volatile uint8_t *buf; /**< Pointer to the completion queue buffer. */
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uint32_t cqe_cnt; /**< Number of entries in the queue. */
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uint32_t cqe_64:1; /**< CQ entry size is 64 bytes. */
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uint32_t cons_index; /**< Last queue entry that was handled. */
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uint32_t cqn; /**< CQ number. */
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int arm_sn; /**< Rx event counter. */
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};
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/**
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* Retrieve a CQE entry from a CQ.
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*
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* cqe = cq->buf + cons_index * cqe_size + cqe_offset
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*
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* Where cqe_size is 32 or 64 bytes and cqe_offset is 0 or 32 (depending on
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* cqe_size).
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*
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* @param cq
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* CQ to retrieve entry from.
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* @param index
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* Entry index.
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*
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* @return
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* Pointer to CQE entry.
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*/
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static inline volatile struct mlx4_cqe *
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mlx4_get_cqe(struct mlx4_cq *cq, uint32_t index)
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{
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return (volatile struct mlx4_cqe *)(cq->buf +
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((index & (cq->cqe_cnt - 1)) <<
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(5 + cq->cqe_64)) +
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(cq->cqe_64 << 5));
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}
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/**
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* Transpose a flag in a value.
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*
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* @param val
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* Input value.
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* @param from
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* Flag to retrieve from input value.
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* @param to
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* Flag to set in output value.
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*
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* @return
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* Output value with transposed flag enabled if present on input.
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*/
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static inline uint64_t
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mlx4_transpose(uint64_t val, uint64_t from, uint64_t to)
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{
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return (from >= to ?
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(val & from) / (from / to) :
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(val & from) * (to / from));
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}
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#endif /* MLX4_PRM_H_ */
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