b6e395692b
Add base support as ROC(Rest of Chip) API which will be used by PMD dmadev driver. This patch adds routines to init, fini, configure the DPI DMA device found in Marvell's CN9k or CN10k SoC families. Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
142 lines
3.2 KiB
C
142 lines
3.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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/**
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* DPI device HW definitions.
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*/
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#ifndef DEV_DPI_HW_H
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#define DEV_DPI_HW_H
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#include <stdint.h>
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/* DPI VF register offsets from VF_BAR0 */
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#define DPI_VDMA_EN (0x0)
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#define DPI_VDMA_REQQ_CTL (0x8)
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#define DPI_VDMA_DBELL (0x10)
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#define DPI_VDMA_SADDR (0x18)
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#define DPI_VDMA_COUNTS (0x20)
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#define DPI_VDMA_NADDR (0x28)
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#define DPI_VDMA_IWBUSY (0x30)
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#define DPI_VDMA_CNT (0x38)
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#define DPI_VF_INT (0x100)
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#define DPI_VF_INT_W1S (0x108)
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#define DPI_VF_INT_ENA_W1C (0x110)
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#define DPI_VF_INT_ENA_W1S (0x118)
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/**
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* Enumeration dpi_hdr_xtype_e
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*
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* DPI Transfer Type Enumeration
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* Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE].
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*/
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#define DPI_XTYPE_OUTBOUND (0)
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#define DPI_XTYPE_INBOUND (1)
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#define DPI_XTYPE_INTERNAL_ONLY (2)
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#define DPI_XTYPE_EXTERNAL_ONLY (3)
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#define DPI_HDR_XTYPE_MASK 0x3
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#define DPI_HDR_PT_ZBW_CA 0x0
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#define DPI_HDR_PT_ZBW_NC 0x1
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#define DPI_HDR_PT_WQP 0x2
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#define DPI_HDR_PT_WQP_NOSTATUS 0x0
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#define DPI_HDR_PT_WQP_STATUSCA 0x1
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#define DPI_HDR_PT_WQP_STATUSNC 0x3
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#define DPI_HDR_PT_CNT 0x3
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#define DPI_HDR_PT_MASK 0x3
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#define DPI_HDR_TT_MASK 0x3
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#define DPI_HDR_GRP_MASK 0x3FF
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#define DPI_HDR_FUNC_MASK 0xFFFF
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/* Big endian data bit position in DMA local pointer */
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#define DPI_LPTR_BED_BIT_POS (60)
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#define DPI_MIN_CMD_SIZE 8
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#define DPI_MAX_CMD_SIZE 64
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/**
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* Structure dpi_instr_hdr_s for CN9K
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*
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* DPI DMA Instruction Header Format
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*/
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union dpi_instr_hdr_s {
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uint64_t u[4];
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struct dpi_dma_instr_hdr_s_s {
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uint64_t tag : 32;
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uint64_t tt : 2;
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uint64_t grp : 10;
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uint64_t reserved_44_47 : 4;
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uint64_t nfst : 4;
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uint64_t reserved_52_53 : 2;
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uint64_t nlst : 4;
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uint64_t reserved_58_63 : 6;
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/* Word 0 - End */
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uint64_t aura : 20;
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uint64_t func : 16;
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uint64_t pt : 2;
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uint64_t reserved_102 : 1;
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uint64_t pvfe : 1;
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uint64_t fl : 1;
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uint64_t ii : 1;
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uint64_t fi : 1;
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uint64_t ca : 1;
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uint64_t csel : 1;
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uint64_t reserved_109_111 : 3;
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uint64_t xtype : 2;
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uint64_t reserved_114_119 : 6;
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uint64_t fport : 2;
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uint64_t reserved_122_123 : 2;
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uint64_t lport : 2;
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uint64_t reserved_126_127 : 2;
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/* Word 1 - End */
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uint64_t ptr : 64;
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/* Word 2 - End */
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uint64_t reserved_192_255 : 64;
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/* Word 3 - End */
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} s;
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};
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/**
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* Structure dpi_cn10k_instr_hdr_s for CN10K
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*
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* DPI DMA Instruction Header Format
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*/
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union dpi_cn10k_instr_hdr_s {
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uint64_t u[4];
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struct dpi_cn10k_dma_instr_hdr_s_s {
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uint64_t nfst : 4;
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uint64_t reserved_4_5 : 2;
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uint64_t nlst : 4;
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uint64_t reserved_10_11 : 2;
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uint64_t pvfe : 1;
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uint64_t reserved_13 : 1;
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uint64_t func : 16;
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uint64_t aura : 20;
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uint64_t xtype : 2;
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uint64_t reserved_52_53 : 2;
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uint64_t pt : 2;
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uint64_t fport : 2;
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uint64_t reserved_58_59 : 2;
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uint64_t lport : 2;
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uint64_t reserved_62_63 : 2;
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/* Word 0 - End */
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uint64_t ptr : 64;
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/* Word 1 - End */
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uint64_t tag : 32;
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uint64_t tt : 2;
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uint64_t grp : 10;
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uint64_t reserved_172_173 : 2;
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uint64_t fl : 1;
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uint64_t ii : 1;
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uint64_t fi : 1;
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uint64_t ca : 1;
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uint64_t csel : 1;
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uint64_t reserved_179_191 : 3;
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/* Word 2 - End */
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uint64_t reserved_192_255 : 64;
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/* Word 3 - End */
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} s;
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};
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#endif /*__DEV_DPI_HW_H__*/
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