fa485faca2
According to the suggestion of our legal department, to standardize the copyright license of our code to avoid potential copyright risks, we make a unified modification to the "Hisilicon", which was nonstandard, in the main modules we maintain. We change it to "HiSilicon", which is consistent with the terms used on the following official website: https://www.hisilicon.com/en/terms-of-use. Fixes: 565829db8b8f ("net/hns3: add build and doc infrastructure") Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Fixes: e31f123db06b ("net/hns3: support NEON Tx") Fixes: c09c7847d892 ("net/hns3: support traffic management") Cc: stable@dpdk.org Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
120 lines
4.2 KiB
C
120 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 HiSilicon Limited.
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*/
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#ifndef _HNS3_INTR_H_
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#define _HNS3_INTR_H_
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#include <stdint.h>
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#include "hns3_ethdev.h"
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#define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
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#define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
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#define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
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#define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
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#define HNS3_PPP_PF_ERR_INT_EN 0x0003
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#define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003
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#define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F
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#define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
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#define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F
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#define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
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#define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF
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#define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
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#define HNS3_MAC_TNL_INT_EN GENMASK(9, 0)
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#define HNS3_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
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#define HNS3_MAC_TNL_INT_CLR GENMASK(9, 0)
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#define HNS3_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
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#define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
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#define HNS3_IMP_ITCM4_ECC_ERR_INT_EN 0x300
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#define HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
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#define HNS3_IMP_RD_POISON_ERR_INT_EN 0x0100
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#define HNS3_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
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#define HNS3_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
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#define HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
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#define HNS3_TQP_ECC_ERR_INT_EN 0x0FFF
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#define HNS3_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
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#define HNS3_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
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#define HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
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#define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
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#define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
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#define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
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#define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
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#define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101
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#define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
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#define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0)
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#define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
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#define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
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#define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
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#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
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#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
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#define HNS3_IGU_ERR_INT_ENABLE 0x0000066F
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#define HNS3_IGU_ERR_INT_DISABLE 0x00000660
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#define HNS3_IGU_ERR_INT_EN_MASK 0x000F
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#define HNS3_IGU_TNL_ERR_INT_EN 0x0002AABF
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#define HNS3_IGU_TNL_ERR_INT_EN_MASK 0x003F
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#define HNS3_NCSI_ERR_INT_EN 0x3
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#define HNS3_TM_SCH_ECC_ERR_INT_EN 0x3
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#define HNS3_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
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#define HNS3_RESET_PROCESS_MS 200
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struct hns3_hw_blk {
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const char *name;
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int (*enable_err_intr)(struct hns3_adapter *hns, bool en);
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};
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struct hns3_hw_error {
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uint32_t int_msk;
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const char *msg;
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enum hns3_reset_level reset_level;
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};
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struct hns3_hw_error_desc {
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uint8_t desc_offset;
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uint8_t data_offset;
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const char *msg;
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const struct hns3_hw_error *hw_err;
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};
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int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);
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void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
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void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);
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void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en);
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void hns3_intr_unregister(const struct rte_intr_handle *hdl,
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rte_intr_callback_fn cb_fn, void *cb_arg);
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void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable);
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int hns3_reset_init(struct hns3_hw *hw);
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void hns3_wait_callback(void *param);
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void hns3_schedule_reset(struct hns3_adapter *hns);
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void hns3_schedule_delayed_reset(struct hns3_adapter *hns);
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int hns3_reset_req_hw_reset(struct hns3_adapter *hns);
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int hns3_reset_process(struct hns3_adapter *hns,
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enum hns3_reset_level reset_level);
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void hns3_reset_abort(struct hns3_adapter *hns);
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#endif /* _HNS3_INTR_H_ */
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