efc52855dc
This patch removes unused fields from structs qat_qp and qat_qp_config, together with their initializations. Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _QAT_QP_H_
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#define _QAT_QP_H_
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#include "qat_common.h"
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#include "adf_transport_access_macros.h"
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struct qat_pci_device;
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#define QAT_CSR_HEAD_WRITE_THRESH 32U
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/* number of requests to accumulate before writing head CSR */
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#define QAT_QP_MIN_INFL_THRESHOLD 256
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/**
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* Structure with data needed for creation of queue pair.
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*/
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struct qat_qp_hw_data {
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enum qat_service_type service_type;
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uint8_t hw_bundle_num;
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uint8_t tx_ring_num;
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uint8_t rx_ring_num;
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uint16_t tx_msg_size;
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uint16_t rx_msg_size;
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};
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/**
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* Structure with data needed for creation of queue pair.
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*/
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struct qat_qp_config {
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const struct qat_qp_hw_data *hw;
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uint32_t nb_descriptors;
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uint32_t cookie_size;
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int socket_id;
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const char *service_str;
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};
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/**
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* Structure associated with each queue.
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*/
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struct qat_queue {
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char memz_name[RTE_MEMZONE_NAMESIZE];
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void *base_addr; /* Base address */
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rte_iova_t base_phys_addr; /* Queue physical address */
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uint32_t head; /* Shadow copy of the head */
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uint32_t tail; /* Shadow copy of the tail */
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uint32_t modulo_mask;
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uint32_t msg_size;
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uint32_t queue_size;
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uint8_t trailz;
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uint8_t hw_bundle_number;
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uint8_t hw_queue_number;
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/* HW queue aka ring offset on bundle */
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uint32_t csr_head; /* last written head value */
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uint32_t csr_tail; /* last written tail value */
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uint16_t nb_processed_responses;
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/* number of responses processed since last CSR head write */
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};
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struct qat_qp {
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void *mmap_bar_addr;
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struct qat_queue tx_q;
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struct qat_queue rx_q;
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struct qat_common_stats stats;
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struct rte_mempool *op_cookie_pool;
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void **op_cookies;
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uint32_t nb_descriptors;
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enum qat_device_gen qat_dev_gen;
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enum qat_service_type service_type;
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struct qat_pci_device *qat_dev;
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/**< qat device this qp is on */
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uint32_t enqueued;
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uint32_t dequeued __rte_aligned(4);
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uint16_t max_inflights;
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uint16_t min_enq_burst_threshold;
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} __rte_cache_aligned;
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extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
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extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
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uint16_t
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qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
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uint16_t
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qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);
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uint16_t
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qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
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int
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qat_qp_release(struct qat_qp **qp_addr);
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int
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qat_qp_setup(struct qat_pci_device *qat_dev,
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struct qat_qp **qp_addr, uint16_t queue_pair_id,
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struct qat_qp_config *qat_qp_conf);
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int
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qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
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enum qat_service_type service);
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int
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qat_cq_get_fw_version(struct qat_qp *qp);
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/* Needed for weak function*/
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int
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qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
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void *op_cookie __rte_unused,
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uint64_t *dequeue_err_count __rte_unused);
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#endif /* _QAT_QP_H_ */
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