2c82554c98
Dev start and stop operations are added. To accomplish this internal functions to enable or disable IO queues are incorporated. Signed-off-by: Nalla Pradeep <pnalla@marvell.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
397 lines
10 KiB
C
397 lines
10 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_io.h>
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#include <ethdev_driver.h>
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#include <ethdev_pci.h>
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#include "otx_ep_common.h"
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#include "otx_ep_vf.h"
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static void
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otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
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{
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volatile uint64_t reg_val = 0ull;
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/* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
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* IS_64B is by default enabled.
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*/
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));
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reg_val |= OTX_EP_R_IN_CTL_RDSIZE;
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reg_val |= OTX_EP_R_IN_CTL_IS_64B;
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reg_val |= OTX_EP_R_IN_CTL_ESR;
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otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_CONTROL(q_no));
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));
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if (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {
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do {
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reg_val = rte_read64(otx_ep->hw_addr +
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OTX_EP_R_IN_CONTROL(q_no));
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} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
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}
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}
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static void
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otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
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{
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volatile uint64_t reg_val = 0ull;
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(q_no));
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reg_val &= ~(OTX_EP_R_OUT_CTL_IMODE);
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reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_P);
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reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_P);
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reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_I);
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reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_I);
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reg_val &= ~(OTX_EP_R_OUT_CTL_ES_I);
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reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_D);
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reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_D);
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reg_val &= ~(OTX_EP_R_OUT_CTL_ES_D);
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/* INFO/DATA ptr swap is required */
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reg_val |= (OTX_EP_R_OUT_CTL_ES_P);
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otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));
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}
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static void
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otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)
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{
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uint64_t q_no = 0ull;
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for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
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otx_ep_setup_global_iq_reg(otx_ep, q_no);
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}
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static void
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otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)
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{
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uint32_t q_no;
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for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
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otx_ep_setup_global_oq_reg(otx_ep, q_no);
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}
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static void
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otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)
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{
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otx_ep_setup_global_input_regs(otx_ep);
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otx_ep_setup_global_output_regs(otx_ep);
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}
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static void
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otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
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{
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struct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];
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volatile uint64_t reg_val = 0ull;
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));
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/* Wait till IDLE to set to 1, not supposed to configure BADDR
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* as long as IDLE is 0
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*/
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if (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {
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do {
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reg_val = rte_read64(otx_ep->hw_addr +
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OTX_EP_R_IN_CONTROL(iq_no));
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} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
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}
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/* Write the start of the input queue's ring and its size */
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otx_ep_write64(iq->base_addr_dma, otx_ep->hw_addr,
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OTX_EP_R_IN_INSTR_BADDR(iq_no));
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otx_ep_write64(iq->nb_desc, otx_ep->hw_addr,
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OTX_EP_R_IN_INSTR_RSIZE(iq_no));
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/* Remember the doorbell & instruction count register addr
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* for this queue
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*/
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iq->doorbell_reg = (uint8_t *)otx_ep->hw_addr +
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OTX_EP_R_IN_INSTR_DBELL(iq_no);
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iq->inst_cnt_reg = (uint8_t *)otx_ep->hw_addr +
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OTX_EP_R_IN_CNTS(iq_no);
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otx_ep_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
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iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
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do {
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reg_val = rte_read32(iq->inst_cnt_reg);
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rte_write32(reg_val, iq->inst_cnt_reg);
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} while (reg_val != 0);
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/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
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* to raise
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*/
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/* reg_val = rte_read64(otx_ep->hw_addr +
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* OTX_EP_R_IN_INT_LEVELS(iq_no));
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*/
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otx_ep_write64(OTX_EP_CLEAR_IN_INT_LVLS, otx_ep->hw_addr,
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OTX_EP_R_IN_INT_LEVELS(iq_no));
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}
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static void
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otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
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{
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volatile uint64_t reg_val = 0ull;
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uint64_t oq_ctl = 0ull;
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struct otx_ep_droq *droq = otx_ep->droq[oq_no];
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/* Wait on IDLE to set to 1, supposed to configure BADDR
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* as log as IDLE is 0
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*/
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otx_ep_write64(0ULL, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(oq_no));
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));
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while (!(reg_val & OTX_EP_R_OUT_CTL_IDLE)) {
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reg_val = rte_read64(otx_ep->hw_addr +
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OTX_EP_R_OUT_CONTROL(oq_no));
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}
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otx_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr,
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OTX_EP_R_OUT_SLIST_BADDR(oq_no));
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otx_ep_write64(droq->nb_desc, otx_ep->hw_addr,
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OTX_EP_R_OUT_SLIST_RSIZE(oq_no));
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oq_ctl = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));
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/* Clear the ISIZE and BSIZE (22-0) */
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oq_ctl &= ~(OTX_EP_CLEAR_ISIZE_BSIZE);
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/* Populate the BSIZE (15-0) */
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oq_ctl |= (droq->buffer_size & OTX_EP_DROQ_BUFSZ_MASK);
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otx_ep_write64(oq_ctl, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(oq_no));
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/* Mapped address of the pkt_sent and pkts_credit regs */
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droq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr +
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OTX_EP_R_OUT_CNTS(oq_no);
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droq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr +
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OTX_EP_R_OUT_SLIST_DBELL(oq_no);
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otx_ep_write64(OTX_EP_CLEAR_OUT_INT_LVLS, otx_ep->hw_addr,
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OTX_EP_R_OUT_INT_LEVELS(oq_no));
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/* Clear the OQ doorbell */
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rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
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while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
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rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
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rte_delay_ms(1);
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}
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otx_ep_dbg("OTX_EP_R[%d]_credit:%x\n", oq_no,
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rte_read32(droq->pkts_credit_reg));
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/* Clear the OQ_OUT_CNTS doorbell */
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reg_val = rte_read32(droq->pkts_sent_reg);
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rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
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otx_ep_dbg("OTX_EP_R[%d]_sent: %x\n", oq_no,
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rte_read32(droq->pkts_sent_reg));
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while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
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reg_val = rte_read32(droq->pkts_sent_reg);
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rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
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rte_delay_ms(1);
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}
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}
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static int
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otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
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{
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uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
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uint64_t reg_val = 0ull;
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/* Resetting doorbells during IQ enabling also to handle abrupt
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* guest reboot. IQ reset does not clear the doorbells.
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*/
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otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,
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OTX_EP_R_IN_INSTR_DBELL(q_no));
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while (((rte_read64(otx_ep->hw_addr +
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OTX_EP_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
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rte_delay_ms(1);
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}
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if (loop == 0) {
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otx_ep_err("dbell reset failed\n");
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return -EIO;
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}
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));
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reg_val |= 0x1ull;
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otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
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otx_ep_info("IQ[%d] enable done\n", q_no);
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return 0;
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}
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static int
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otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
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{
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uint64_t reg_val = 0ull;
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uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
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/* Resetting doorbells during IQ enabling also to handle abrupt
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* guest reboot. IQ reset does not clear the doorbells.
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*/
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otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,
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OTX_EP_R_OUT_SLIST_DBELL(q_no));
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while (((rte_read64(otx_ep->hw_addr +
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OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) {
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rte_delay_ms(1);
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}
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if (loop == 0) {
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otx_ep_err("dbell reset failed\n");
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return -EIO;
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}
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));
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reg_val |= 0x1ull;
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otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
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otx_ep_info("OQ[%d] enable done\n", q_no);
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return 0;
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}
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static int
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otx_ep_enable_io_queues(struct otx_ep_device *otx_ep)
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{
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uint32_t q_no = 0;
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int ret;
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for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {
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ret = otx_ep_enable_iq(otx_ep, q_no);
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if (ret)
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return ret;
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}
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for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++) {
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ret = otx_ep_enable_oq(otx_ep, q_no);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void
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otx_ep_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
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{
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uint64_t reg_val = 0ull;
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/* Reset the doorbell register for this Input Queue. */
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));
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reg_val &= ~0x1ull;
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otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
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}
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static void
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otx_ep_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
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{
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uint64_t reg_val = 0ull;
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));
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reg_val &= ~0x1ull;
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otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
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}
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static void
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otx_ep_disable_io_queues(struct otx_ep_device *otx_ep)
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{
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uint32_t q_no = 0;
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for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
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otx_ep_disable_iq(otx_ep, q_no);
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otx_ep_disable_oq(otx_ep, q_no);
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}
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}
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/* OTX_EP default configuration */
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static const struct otx_ep_config default_otx_ep_conf = {
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/* IQ attributes */
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.iq = {
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.max_iqs = OTX_EP_CFG_IO_QUEUES,
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.instr_type = OTX_EP_64BYTE_INSTR,
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.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
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OTX_EP_CFG_IO_QUEUES),
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},
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/* OQ attributes */
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.oq = {
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.max_oqs = OTX_EP_CFG_IO_QUEUES,
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.info_ptr = OTX_EP_OQ_INFOPTR_MODE,
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.refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,
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},
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.num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,
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.num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,
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.oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,
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};
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static const struct otx_ep_config*
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otx_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
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{
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const struct otx_ep_config *default_conf = NULL;
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default_conf = &default_otx_ep_conf;
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return default_conf;
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}
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int
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otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)
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{
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uint64_t reg_val = 0ull;
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/* If application doesn't provide its conf, use driver default conf */
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if (otx_ep->conf == NULL) {
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otx_ep->conf = otx_ep_get_defconf(otx_ep);
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if (otx_ep->conf == NULL) {
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otx_ep_err("OTX_EP VF default config not found\n");
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return -ENOENT;
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}
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otx_ep_info("Default config is used\n");
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}
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/* Get IOQs (RPVF] count */
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reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(0));
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otx_ep->sriov_info.rings_per_vf = ((reg_val >> OTX_EP_R_IN_CTL_RPVF_POS)
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& OTX_EP_R_IN_CTL_RPVF_MASK);
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otx_ep_info("OTX_EP RPVF: %d\n", otx_ep->sriov_info.rings_per_vf);
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otx_ep->fn_list.setup_iq_regs = otx_ep_setup_iq_regs;
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otx_ep->fn_list.setup_oq_regs = otx_ep_setup_oq_regs;
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otx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;
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otx_ep->fn_list.enable_io_queues = otx_ep_enable_io_queues;
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otx_ep->fn_list.disable_io_queues = otx_ep_disable_io_queues;
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otx_ep->fn_list.enable_iq = otx_ep_enable_iq;
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otx_ep->fn_list.disable_iq = otx_ep_disable_iq;
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otx_ep->fn_list.enable_oq = otx_ep_enable_oq;
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otx_ep->fn_list.disable_oq = otx_ep_disable_oq;
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return 0;
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}
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