99a2dd955f
There is no reason for the DPDK libraries to all have 'librte_' prefix on the directory names. This prefix makes the directory names longer and also makes it awkward to add features referring to individual libraries in the build - should the lib names be specified with or without the prefix. Therefore, we can just remove the library prefix and use the library's unique name as the directory name, i.e. 'eal' rather than 'librte_eal' Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
283 lines
6.4 KiB
C
283 lines
6.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2014 Intel Corporation
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*/
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#ifndef _RTE_ATOMIC_X86_H_
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#define _RTE_ATOMIC_X86_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <rte_common.h>
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#include <rte_config.h>
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#include <emmintrin.h>
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#include "generic/rte_atomic.h"
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#if RTE_MAX_LCORE == 1
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#define MPLOCKED /**< No need to insert MP lock prefix. */
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#else
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#define MPLOCKED "lock ; " /**< Insert MP lock prefix. */
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#endif
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#define rte_mb() _mm_mfence()
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#define rte_wmb() _mm_sfence()
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#define rte_rmb() _mm_lfence()
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#define rte_smp_wmb() rte_compiler_barrier()
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#define rte_smp_rmb() rte_compiler_barrier()
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/*
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* From Intel Software Development Manual; Vol 3;
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* 8.2.2 Memory Ordering in P6 and More Recent Processor Families:
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* ...
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* . Reads are not reordered with other reads.
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* . Writes are not reordered with older reads.
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* . Writes to memory are not reordered with other writes,
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* with the following exceptions:
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* . streaming stores (writes) executed with the non-temporal move
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* instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); and
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* . string operations (see Section 8.2.4.1).
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* ...
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* . Reads may be reordered with older writes to different locations but not
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* with older writes to the same location.
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* . Reads or writes cannot be reordered with I/O instructions,
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* locked instructions, or serializing instructions.
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* . Reads cannot pass earlier LFENCE and MFENCE instructions.
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* . Writes ... cannot pass earlier LFENCE, SFENCE, and MFENCE instructions.
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* . LFENCE instructions cannot pass earlier reads.
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* . SFENCE instructions cannot pass earlier writes ...
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* . MFENCE instructions cannot pass earlier reads, writes ...
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*
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* As pointed by Java guys, that makes possible to use lock-prefixed
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* instructions to get the same effect as mfence and on most modern HW
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* that gives a better performance then using mfence:
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* https://shipilev.net/blog/2014/on-the-fence-with-dependencies/
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* Basic idea is to use lock prefixed add with some dummy memory location
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* as the destination. From their experiments 128B(2 cache lines) below
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* current stack pointer looks like a good candidate.
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* So below we use that techinque for rte_smp_mb() implementation.
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*/
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static __rte_always_inline void
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rte_smp_mb(void)
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{
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#ifdef RTE_ARCH_I686
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asm volatile("lock addl $0, -128(%%esp); " ::: "memory");
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#else
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asm volatile("lock addl $0, -128(%%rsp); " ::: "memory");
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#endif
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}
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#define rte_io_mb() rte_mb()
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#define rte_io_wmb() rte_compiler_barrier()
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#define rte_io_rmb() rte_compiler_barrier()
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/**
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* Synchronization fence between threads based on the specified memory order.
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*
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* On x86 the __atomic_thread_fence(__ATOMIC_SEQ_CST) generates full 'mfence'
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* which is quite expensive. The optimized implementation of rte_smp_mb is
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* used instead.
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*/
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static __rte_always_inline void
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rte_atomic_thread_fence(int memorder)
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{
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if (memorder == __ATOMIC_SEQ_CST)
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rte_smp_mb();
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else
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__atomic_thread_fence(memorder);
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}
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/*------------------------- 16 bit atomic operations -------------------------*/
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#ifndef RTE_FORCE_INTRINSICS
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static inline int
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rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
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{
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uint8_t res;
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asm volatile(
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MPLOCKED
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"cmpxchgw %[src], %[dst];"
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"sete %[res];"
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: [res] "=a" (res), /* output */
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[dst] "=m" (*dst)
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: [src] "r" (src), /* input */
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"a" (exp),
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"m" (*dst)
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: "memory"); /* no-clobber list */
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return res;
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}
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static inline uint16_t
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rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
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{
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asm volatile(
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MPLOCKED
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"xchgw %0, %1;"
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: "=r" (val), "=m" (*dst)
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: "0" (val), "m" (*dst)
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: "memory"); /* no-clobber list */
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return val;
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}
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static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
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{
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return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
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}
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static inline void
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rte_atomic16_inc(rte_atomic16_t *v)
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{
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asm volatile(
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MPLOCKED
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"incw %[cnt]"
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: [cnt] "=m" (v->cnt) /* output */
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: "m" (v->cnt) /* input */
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);
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}
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static inline void
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rte_atomic16_dec(rte_atomic16_t *v)
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{
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asm volatile(
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MPLOCKED
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"decw %[cnt]"
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: [cnt] "=m" (v->cnt) /* output */
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: "m" (v->cnt) /* input */
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);
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}
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static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
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{
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uint8_t ret;
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asm volatile(
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MPLOCKED
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"incw %[cnt] ; "
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"sete %[ret]"
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: [cnt] "+m" (v->cnt), /* output */
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[ret] "=qm" (ret)
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);
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return ret != 0;
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}
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static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
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{
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uint8_t ret;
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asm volatile(MPLOCKED
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"decw %[cnt] ; "
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"sete %[ret]"
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: [cnt] "+m" (v->cnt), /* output */
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[ret] "=qm" (ret)
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);
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return ret != 0;
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}
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/*------------------------- 32 bit atomic operations -------------------------*/
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static inline int
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rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
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{
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uint8_t res;
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asm volatile(
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MPLOCKED
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"cmpxchgl %[src], %[dst];"
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"sete %[res];"
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: [res] "=a" (res), /* output */
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[dst] "=m" (*dst)
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: [src] "r" (src), /* input */
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"a" (exp),
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"m" (*dst)
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: "memory"); /* no-clobber list */
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return res;
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}
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static inline uint32_t
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rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
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{
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asm volatile(
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MPLOCKED
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"xchgl %0, %1;"
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: "=r" (val), "=m" (*dst)
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: "0" (val), "m" (*dst)
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: "memory"); /* no-clobber list */
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return val;
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}
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static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
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{
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return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
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}
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static inline void
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rte_atomic32_inc(rte_atomic32_t *v)
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{
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asm volatile(
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MPLOCKED
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"incl %[cnt]"
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: [cnt] "=m" (v->cnt) /* output */
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: "m" (v->cnt) /* input */
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);
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}
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static inline void
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rte_atomic32_dec(rte_atomic32_t *v)
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{
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asm volatile(
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MPLOCKED
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"decl %[cnt]"
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: [cnt] "=m" (v->cnt) /* output */
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: "m" (v->cnt) /* input */
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);
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}
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static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
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{
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uint8_t ret;
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asm volatile(
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MPLOCKED
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"incl %[cnt] ; "
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"sete %[ret]"
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: [cnt] "+m" (v->cnt), /* output */
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[ret] "=qm" (ret)
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);
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return ret != 0;
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}
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static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
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{
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uint8_t ret;
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asm volatile(MPLOCKED
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"decl %[cnt] ; "
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"sete %[ret]"
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: [cnt] "+m" (v->cnt), /* output */
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[ret] "=qm" (ret)
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);
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return ret != 0;
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}
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#endif
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#ifdef RTE_ARCH_I686
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#include "rte_atomic_32.h"
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#else
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#include "rte_atomic_64.h"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_ATOMIC_X86_H_ */
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