99a2dd955f
There is no reason for the DPDK libraries to all have 'librte_' prefix on the directory names. This prefix makes the directory names longer and also makes it awkward to add features referring to individual libraries in the build - should the lib names be specified with or without the prefix. Therefore, we can just remove the library prefix and use the library's unique name as the directory name, i.e. 'eal' rather than 'librte_eal' Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
148 lines
6.3 KiB
C
148 lines
6.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2014 Intel Corporation
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*/
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#ifndef _RTE_CPUFLAGS_X86_64_H_
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#define _RTE_CPUFLAGS_X86_64_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum rte_cpu_flag_t {
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/* (EAX 01h) ECX features*/
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RTE_CPUFLAG_SSE3 = 0, /**< SSE3 */
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RTE_CPUFLAG_PCLMULQDQ, /**< PCLMULQDQ */
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RTE_CPUFLAG_DTES64, /**< DTES64 */
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RTE_CPUFLAG_MONITOR, /**< MONITOR */
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RTE_CPUFLAG_DS_CPL, /**< DS_CPL */
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RTE_CPUFLAG_VMX, /**< VMX */
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RTE_CPUFLAG_SMX, /**< SMX */
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RTE_CPUFLAG_EIST, /**< EIST */
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RTE_CPUFLAG_TM2, /**< TM2 */
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RTE_CPUFLAG_SSSE3, /**< SSSE3 */
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RTE_CPUFLAG_CNXT_ID, /**< CNXT_ID */
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RTE_CPUFLAG_FMA, /**< FMA */
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RTE_CPUFLAG_CMPXCHG16B, /**< CMPXCHG16B */
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RTE_CPUFLAG_XTPR, /**< XTPR */
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RTE_CPUFLAG_PDCM, /**< PDCM */
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RTE_CPUFLAG_PCID, /**< PCID */
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RTE_CPUFLAG_DCA, /**< DCA */
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RTE_CPUFLAG_SSE4_1, /**< SSE4_1 */
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RTE_CPUFLAG_SSE4_2, /**< SSE4_2 */
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RTE_CPUFLAG_X2APIC, /**< X2APIC */
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RTE_CPUFLAG_MOVBE, /**< MOVBE */
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RTE_CPUFLAG_POPCNT, /**< POPCNT */
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RTE_CPUFLAG_TSC_DEADLINE, /**< TSC_DEADLINE */
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RTE_CPUFLAG_AES, /**< AES */
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RTE_CPUFLAG_XSAVE, /**< XSAVE */
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RTE_CPUFLAG_OSXSAVE, /**< OSXSAVE */
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RTE_CPUFLAG_AVX, /**< AVX */
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RTE_CPUFLAG_F16C, /**< F16C */
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RTE_CPUFLAG_RDRAND, /**< RDRAND */
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RTE_CPUFLAG_HYPERVISOR, /**< Running in a VM */
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/* (EAX 01h) EDX features */
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RTE_CPUFLAG_FPU, /**< FPU */
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RTE_CPUFLAG_VME, /**< VME */
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RTE_CPUFLAG_DE, /**< DE */
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RTE_CPUFLAG_PSE, /**< PSE */
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RTE_CPUFLAG_TSC, /**< TSC */
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RTE_CPUFLAG_MSR, /**< MSR */
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RTE_CPUFLAG_PAE, /**< PAE */
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RTE_CPUFLAG_MCE, /**< MCE */
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RTE_CPUFLAG_CX8, /**< CX8 */
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RTE_CPUFLAG_APIC, /**< APIC */
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RTE_CPUFLAG_SEP, /**< SEP */
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RTE_CPUFLAG_MTRR, /**< MTRR */
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RTE_CPUFLAG_PGE, /**< PGE */
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RTE_CPUFLAG_MCA, /**< MCA */
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RTE_CPUFLAG_CMOV, /**< CMOV */
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RTE_CPUFLAG_PAT, /**< PAT */
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RTE_CPUFLAG_PSE36, /**< PSE36 */
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RTE_CPUFLAG_PSN, /**< PSN */
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RTE_CPUFLAG_CLFSH, /**< CLFSH */
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RTE_CPUFLAG_DS, /**< DS */
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RTE_CPUFLAG_ACPI, /**< ACPI */
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RTE_CPUFLAG_MMX, /**< MMX */
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RTE_CPUFLAG_FXSR, /**< FXSR */
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RTE_CPUFLAG_SSE, /**< SSE */
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RTE_CPUFLAG_SSE2, /**< SSE2 */
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RTE_CPUFLAG_SS, /**< SS */
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RTE_CPUFLAG_HTT, /**< HTT */
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RTE_CPUFLAG_TM, /**< TM */
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RTE_CPUFLAG_PBE, /**< PBE */
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/* (EAX 06h) EAX features */
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RTE_CPUFLAG_DIGTEMP, /**< DIGTEMP */
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RTE_CPUFLAG_TRBOBST, /**< TRBOBST */
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RTE_CPUFLAG_ARAT, /**< ARAT */
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RTE_CPUFLAG_PLN, /**< PLN */
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RTE_CPUFLAG_ECMD, /**< ECMD */
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RTE_CPUFLAG_PTM, /**< PTM */
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/* (EAX 06h) ECX features */
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RTE_CPUFLAG_MPERF_APERF_MSR, /**< MPERF_APERF_MSR */
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RTE_CPUFLAG_ACNT2, /**< ACNT2 */
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RTE_CPUFLAG_ENERGY_EFF, /**< ENERGY_EFF */
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/* (EAX 07h, ECX 0h) EBX features */
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RTE_CPUFLAG_FSGSBASE, /**< FSGSBASE */
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RTE_CPUFLAG_BMI1, /**< BMI1 */
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RTE_CPUFLAG_HLE, /**< Hardware Lock elision */
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RTE_CPUFLAG_AVX2, /**< AVX2 */
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RTE_CPUFLAG_SMEP, /**< SMEP */
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RTE_CPUFLAG_BMI2, /**< BMI2 */
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RTE_CPUFLAG_ERMS, /**< ERMS */
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RTE_CPUFLAG_INVPCID, /**< INVPCID */
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RTE_CPUFLAG_RTM, /**< Transactional memory */
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RTE_CPUFLAG_AVX512F, /**< AVX512F */
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RTE_CPUFLAG_RDSEED, /**< RDSEED instruction */
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/* (EAX 80000001h) ECX features */
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RTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */
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RTE_CPUFLAG_LZCNT, /**< LZCNT */
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/* (EAX 80000001h) EDX features */
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RTE_CPUFLAG_SYSCALL, /**< SYSCALL */
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RTE_CPUFLAG_XD, /**< XD */
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RTE_CPUFLAG_1GB_PG, /**< 1GB_PG */
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RTE_CPUFLAG_RDTSCP, /**< RDTSCP */
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RTE_CPUFLAG_EM64T, /**< EM64T */
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/* (EAX 80000007h) EDX features */
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RTE_CPUFLAG_INVTSC, /**< INVTSC */
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RTE_CPUFLAG_AVX512DQ, /**< AVX512 Doubleword and Quadword */
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RTE_CPUFLAG_AVX512IFMA, /**< AVX512 Integer Fused Multiply-Add */
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RTE_CPUFLAG_AVX512CD, /**< AVX512 Conflict Detection*/
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RTE_CPUFLAG_AVX512BW, /**< AVX512 Byte and Word */
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RTE_CPUFLAG_AVX512VL, /**< AVX512 Vector Length */
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RTE_CPUFLAG_AVX512VBMI, /**< AVX512 Vector Bit Manipulation */
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RTE_CPUFLAG_AVX512VBMI2, /**< AVX512 Vector Bit Manipulation 2 */
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RTE_CPUFLAG_GFNI, /**< Galois Field New Instructions */
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RTE_CPUFLAG_VAES, /**< Vector AES */
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RTE_CPUFLAG_VPCLMULQDQ, /**< Vector Carry-less Multiply */
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RTE_CPUFLAG_AVX512VNNI,
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/**< AVX512 Vector Neural Network Instructions */
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RTE_CPUFLAG_AVX512BITALG, /**< AVX512 Bit Algorithms */
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RTE_CPUFLAG_AVX512VPOPCNTDQ, /**< AVX512 Vector Popcount */
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RTE_CPUFLAG_CLDEMOTE, /**< Cache Line Demote */
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RTE_CPUFLAG_MOVDIRI, /**< Direct Store Instructions */
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RTE_CPUFLAG_MOVDIR64B, /**< Direct Store Instructions 64B */
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RTE_CPUFLAG_AVX512VP2INTERSECT, /**< AVX512 Two Register Intersection */
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RTE_CPUFLAG_WAITPKG, /**< UMONITOR/UMWAIT/TPAUSE */
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/* The last item */
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RTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */
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};
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#include "generic/rte_cpuflags.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_CPUFLAGS_X86_64_H_ */
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