c6b5715746
All drivers should have SPDX on the first line of the source files in the format /* SPDX-License-Identifier: ... Several files used minor modifications which were inconsistent with the pattern. Fix it to make scanning tools easier. Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2017 NXP
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*/
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#ifndef __DPAA2_EVENTDEV_H__
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#define __DPAA2_EVENTDEV_H__
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#include <rte_eventdev_pmd.h>
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#include <rte_eventdev_pmd_vdev.h>
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#include <rte_atomic.h>
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#include <mc/fsl_dpcon.h>
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#include <mc/fsl_mc_sys.h>
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#define EVENTDEV_NAME_DPAA2_PMD event_dpaa2
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#define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0
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#define DPAA2_EVENT_MAX_QUEUES 16
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#define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT 1
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#define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT (UINT32_MAX - 1)
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#define DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS 100UL
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#define DPAA2_EVENT_MAX_QUEUE_FLOWS 2048
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#define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8
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#define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS 0
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#define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH 8
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#define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH 8
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#define DPAA2_EVENT_MAX_NUM_EVENTS (INT32_MAX - 1)
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#define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS 2048
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#define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES 2048
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enum {
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DPAA2_EVENT_DPCI_PARALLEL_QUEUE,
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DPAA2_EVENT_DPCI_ATOMIC_QUEUE,
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DPAA2_EVENT_DPCI_MAX_QUEUES
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};
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#define RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP \
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(RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \
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RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \
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RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID)
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/**< Crypto Rx adapter cap to return If the packet transfers from
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* the cryptodev to eventdev with DPAA2 devices.
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*/
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#define RTE_EVENT_CRYPTO_ADAPTER_DPAA2_CAP \
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(RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW | \
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RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | \
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RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA)
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/**< Ethernet Rx adapter cap to return If the packet transfers from
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* the ethdev to eventdev with DPAA2 devices.
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*/
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struct dpaa2_dpcon_dev {
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TAILQ_ENTRY(dpaa2_dpcon_dev) next;
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struct fsl_mc_io dpcon;
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uint16_t token;
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rte_atomic16_t in_use;
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uint32_t dpcon_id;
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uint16_t qbman_ch_id;
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uint8_t num_priorities;
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uint8_t channel_index;
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};
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struct dpaa2_eventq {
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/* DPcon device */
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struct dpaa2_dpcon_dev *dpcon;
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/* Attached DPCI device */
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struct dpaa2_dpci_dev *dpci;
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/* Mapped event port */
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struct dpaa2_io_portal_t *event_port;
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/* Configuration provided by the user */
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uint32_t event_queue_cfg;
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uint32_t event_queue_id;
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};
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struct dpaa2_port {
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struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES];
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uint8_t num_linked_evq;
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uint8_t is_port_linked;
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uint64_t timeout_us;
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};
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struct dpaa2_eventdev {
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struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES];
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uint32_t dequeue_timeout_ns;
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uint8_t max_event_queues;
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uint8_t nb_event_queues;
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uint8_t nb_event_ports;
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uint8_t resvd_1;
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uint32_t nb_event_queue_flows;
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uint32_t nb_event_port_dequeue_depth;
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uint32_t nb_event_port_enqueue_depth;
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uint32_t event_dev_cfg;
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};
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struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
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void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon);
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#endif /* __DPAA2_EVENTDEV_H__ */
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