numam-dpdk/drivers
Heinrich Kuhn c0a8b02475 net/nfp: read chip model from PluDevice register
For newer smartNIC NVRAM versions the chip model should be read from the
PluDevice register as it provides the authoritative chip model/revision.
This method of reading the chip model is backwards compatible with
legacy NVRAM versions too.

Since the model number is purely used for reporting purposes, follow the
hardware team convention of subtracting 0x10 from the PluDevice register
to obtain the chip model/revision number.

Fixes: c7e9729da6 ("net/nfp: support CPP")
Cc: stable@dpdk.org

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@netronome.com>
Reviewed-by: Louis Peens <louis.peens@netronome.com>
2021-01-29 18:16:12 +01:00
..
baseband config: remove compatibility build defines 2021-01-20 01:43:25 +01:00
bus bus/vdev: add driver IOVA VA mode requirement 2021-01-29 18:16:09 +01:00
common common/mlx5: add GTP TEID modification ID 2021-01-29 18:16:11 +01:00
compress compress/mlx5: add supported capabilities 2021-01-27 20:40:03 +01:00
crypto crypto/dpaa2_sec: fix memory allocation check 2021-01-27 20:58:14 +01:00
event eventdev: make driver-only headers private 2021-01-29 20:59:09 +01:00
mempool ethdev: make driver-only headers private 2021-01-29 20:59:09 +01:00
net net/nfp: read chip model from PluDevice register 2021-01-29 18:16:12 +01:00
raw raw/ioat: fix driver name in secondary process 2021-01-27 13:42:40 +01:00
regex config: remove compatibility build defines 2021-01-20 01:43:25 +01:00
vdpa vdpa/mlx5: fix configuration mutex cleanup 2021-01-29 18:16:10 +01:00
meson.build build: enable pmdinfogen for Windows 2021-01-25 23:24:38 +01:00