numam-dpdk/drivers/net/mlx5/meson.build
Xiaoyu Min 4d368e1da3 net/mlx5: support flow counter action for HWS
This commit adds HW steering counter action support.
The pool mechanism is the basic data structure for the HW steering
counter.

The HW steering's counter pool is based on the rte_ring of zero-copy
variation.

There are two global rte_rings:
1. free_list:
     Store the counters indexes, which are ready for use.
2. wait_reset_list:
     Store the counters indexes, which are just freed from the user and
     need to query the hardware counter to get the reset value before
     this counter can be reused again.

The counter pool also supports cache per HW steering's queues, which are
also based on the rte_ring of zero-copy variation.

The cache can be configured in size, preload, threshold, and fetch size,
they are all exposed via device args.

The main operations of the counter pool are as follows:

 - Get one counter from the pool:
   1. The user call _get_* API.
   2. If the cache is enabled, dequeue one counter index from the local
      cache:
      2. A: if the dequeued one from the local cache is still in reset
        status (counter's query_gen_when_free is equal to pool's query
        gen):
        I. Flush all counters in the local cache back to global
           wait_reset_list.
        II. Fetch _fetch_sz_ counters into the cache from the global
            free list.
        III. Fetch one counter from the cache.
   3. If the cache is empty, fetch _fetch_sz_ counters from the global
      free list into the cache and fetch one counter from the cache.
 - Free one counter into the pool:
   1. The user calls _put_* API.
   2. Put the counter into the local cache.
   3. If the local cache is full:
      A: Write back all counters above _threshold_ into the global
         wait_reset_list.
      B: Also, write back this counter into the global wait_reset_list.

When the local cache is disabled, _get_/_put_ cache directly from/into
global list.

Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-26 13:33:39 +02:00

79 lines
1.8 KiB
Meson

# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018 6WIND S.A.
# Copyright 2018 Mellanox Technologies, Ltd
if not (is_linux or is_windows)
build = false
reason = 'only supported on Linux and Windows'
subdir_done()
endif
deps += ['hash', 'common_mlx5']
headers = files('rte_pmd_mlx5.h')
sources = files(
'mlx5.c',
'mlx5_ethdev.c',
'mlx5_flow.c',
'mlx5_flow_meter.c',
'mlx5_flow_dv.c',
'mlx5_flow_aso.c',
'mlx5_flow_flex.c',
'mlx5_mac.c',
'mlx5_rss.c',
'mlx5_rx.c',
'mlx5_rxmode.c',
'mlx5_rxq.c',
'mlx5_rxtx.c',
'mlx5_stats.c',
'mlx5_trigger.c',
'mlx5_tx.c',
'mlx5_tx_empw.c',
'mlx5_tx_mpw.c',
'mlx5_tx_nompw.c',
'mlx5_tx_txpp.c',
'mlx5_txq.c',
'mlx5_txpp.c',
'mlx5_vlan.c',
'mlx5_utils.c',
'mlx5_devx.c',
)
if is_linux
sources += files(
'mlx5_flow_hw.c',
'mlx5_hws_cnt.c',
'mlx5_flow_verbs.c',
)
if (dpdk_conf.has('RTE_ARCH_X86_64')
or dpdk_conf.has('RTE_ARCH_ARM64')
or dpdk_conf.has('RTE_ARCH_PPC_64'))
sources += files('mlx5_rxtx_vec.c')
endif
endif
cflags_options = [
'-std=c11',
'-Wno-strict-prototypes',
'-D_BSD_SOURCE',
'-D_DEFAULT_SOURCE',
'-D_XOPEN_SOURCE=600',
]
foreach option:cflags_options
if cc.has_argument(option)
cflags += option
endif
endforeach
if get_option('buildtype').contains('debug')
cflags += [ '-pedantic', '-DPEDANTIC' ]
else
cflags += [ '-UPEDANTIC' ]
endif
testpmd_sources += files('mlx5_testpmd.c')
subdir(exec_env)
if (is_linux and mlx5_config.get('HAVE_IBV_FLOW_DV_SUPPORT', false))
subdir('hws')
endif