a3d6026711
The initial objective of
commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
was to add an empty cache line between the producer and consumer
data (on platform with cache line size = 64B), preventing from
having them on adjacent cache lines.
Following discussion on the mailing list, it appears that this
also imposes an alignment constraint that is not required.
This patch removes the extra alignment constraint and adds the
empty cache lines using padding fields in the structure. The
size of rte_ring structure and the offset of the fields remain
the same on platforms with cache line size = 64B:
rte_ring = 384
rte_ring.name = 0
rte_ring.flags = 32
rte_ring.memzone = 40
rte_ring.size = 48
rte_ring.mask = 52
rte_ring.prod = 128
rte_ring.cons = 256
But it has an impact on platform where cache line size is 128B:
rte_ring = 384 -> 768
rte_ring.name = 0
rte_ring.flags = 32
rte_ring.memzone = 40
rte_ring.size = 48
rte_ring.mask = 52
rte_ring.prod = 128 -> 256
rte_ring.cons = 256 -> 512
Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
25 lines
511 B
Makefile
25 lines
511 B
Makefile
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2010-2014 Intel Corporation
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include $(RTE_SDK)/mk/rte.vars.mk
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# library name
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LIB = librte_ring.a
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CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3
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LDLIBS += -lrte_eal
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EXPORT_MAP := rte_ring_version.map
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LIBABIVER := 2
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# all source are stored in SRCS-y
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SRCS-$(CONFIG_RTE_LIBRTE_RING) := rte_ring.c
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# install includes
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SYMLINK-$(CONFIG_RTE_LIBRTE_RING)-include := rte_ring.h \
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rte_ring_generic.h \
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rte_ring_c11_mem.h
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include $(RTE_SDK)/mk/rte.lib.mk
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