305ca2c4c3
Add multi segment Tx vector routine. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
59 lines
1.3 KiB
Meson
59 lines
1.3 KiB
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(C) 2021 Marvell.
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#
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if not dpdk_conf.get('RTE_ARCH_64')
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build = false
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reason = 'only supported on 64-bit'
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subdir_done()
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endif
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sources = files(
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'cnxk_ethdev.c',
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'cnxk_ethdev_devargs.c',
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'cnxk_ethdev_ops.c',
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'cnxk_link.c',
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'cnxk_lookup.c',
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'cnxk_ptp.c',
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'cnxk_rte_flow.c',
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'cnxk_stats.c',
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)
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# CN9K
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sources += files(
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'cn9k_ethdev.c',
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'cn9k_rte_flow.c',
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'cn9k_rx.c',
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'cn9k_rx_mseg.c',
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'cn9k_rx_vec.c',
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'cn9k_rx_vec_mseg.c',
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'cn9k_tx.c',
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'cn9k_tx_mseg.c',
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'cn9k_tx_vec.c',
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'cn9k_tx_vec_mseg.c',
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)
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# CN10K
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sources += files(
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'cn10k_ethdev.c',
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'cn10k_rte_flow.c',
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'cn10k_rx.c',
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'cn10k_rx_mseg.c',
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'cn10k_rx_vec.c',
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'cn10k_rx_vec_mseg.c',
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'cn10k_tx.c',
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'cn10k_tx_mseg.c',
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'cn10k_tx_vec.c',
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'cn10k_tx_vec_mseg.c',
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)
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deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']
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deps += ['common_cnxk', 'mempool_cnxk']
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# Allow implicit vector conversions and strict aliasing warning
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extra_flags = ['-flax-vector-conversions', '-Wno-strict-aliasing']
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foreach flag: extra_flags
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if cc.has_argument(flag)
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cflags += flag
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endif
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endforeach
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