df96fd0d73
The rte_ethdev_driver.h, rte_ethdev_vdev.h and rte_ethdev_pci.h files are for drivers only and should be a private to DPDK and not installed. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com> Acked-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Steven Webster <steven.webster@windriver.com>
976 lines
26 KiB
C
976 lines
26 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2016 Intel Corporation
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*/
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#include <stdio.h>
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#include <errno.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <stdarg.h>
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#include <inttypes.h>
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#include <rte_interrupts.h>
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#include <rte_log.h>
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#include <rte_debug.h>
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#include <rte_eal.h>
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#include <rte_ether.h>
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#include <ethdev_driver.h>
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#include <rte_memcpy.h>
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#include <rte_malloc.h>
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#include <rte_random.h>
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#include "base/ixgbe_common.h"
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#include "ixgbe_ethdev.h"
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#include "rte_pmd_ixgbe.h"
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#define IXGBE_MAX_VFTA (128)
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#define IXGBE_VF_MSG_SIZE_DEFAULT 1
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#define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
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#define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
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static inline uint16_t
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dev_num_vf(struct rte_eth_dev *eth_dev)
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{
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
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return pci_dev->max_vfs;
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}
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static inline
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int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
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{
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unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN];
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struct ixgbe_vf_info *vfinfo =
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*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
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uint16_t vfn;
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for (vfn = 0; vfn < vf_num; vfn++) {
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rte_eth_random_addr(vf_mac_addr);
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/* keep the random address as default */
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memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
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RTE_ETHER_ADDR_LEN);
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}
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return 0;
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}
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static inline int
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ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
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{
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struct ixgbe_interrupt *intr =
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IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
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intr->mask |= IXGBE_EICR_MAILBOX;
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return 0;
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}
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int ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
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{
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struct ixgbe_vf_info **vfinfo =
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IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
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struct ixgbe_mirror_info *mirror_info =
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IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
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struct ixgbe_uta_info *uta_info =
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IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
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struct ixgbe_hw *hw =
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IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
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uint16_t vf_num;
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uint8_t nb_queue;
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int ret = 0;
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PMD_INIT_FUNC_TRACE();
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RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
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vf_num = dev_num_vf(eth_dev);
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if (vf_num == 0)
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return ret;
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*vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
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if (*vfinfo == NULL) {
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PMD_INIT_LOG(ERR,
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"Cannot allocate memory for private VF data");
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return -ENOMEM;
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}
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ret = rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id);
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if (ret) {
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PMD_INIT_LOG(ERR,
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"failed to allocate switch domain for device %d", ret);
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rte_free(*vfinfo);
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*vfinfo = NULL;
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return ret;
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}
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memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
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memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
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hw->mac.mc_filter_type = 0;
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if (vf_num >= ETH_32_POOLS) {
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nb_queue = 2;
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RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
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} else if (vf_num >= ETH_16_POOLS) {
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nb_queue = 4;
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RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
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} else {
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nb_queue = 8;
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RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
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}
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RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
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RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
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RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
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ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
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/* init_mailbox_params */
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hw->mbx.ops.init_params(hw);
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/* set mb interrupt mask */
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ixgbe_mb_intr_setup(eth_dev);
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return ret;
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}
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void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
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{
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struct ixgbe_vf_info **vfinfo;
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uint16_t vf_num;
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int ret;
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PMD_INIT_FUNC_TRACE();
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RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
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RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
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RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
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RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
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vf_num = dev_num_vf(eth_dev);
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if (vf_num == 0)
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return;
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vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
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if (*vfinfo == NULL)
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return;
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ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id);
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if (ret)
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PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
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rte_free(*vfinfo);
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*vfinfo = NULL;
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}
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static void
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ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
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{
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struct ixgbe_hw *hw =
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IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
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struct ixgbe_filter_info *filter_info =
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IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
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uint16_t vf_num;
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int i;
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struct ixgbe_ethertype_filter ethertype_filter;
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if (!hw->mac.ops.set_ethertype_anti_spoofing) {
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PMD_DRV_LOG(INFO, "ether type anti-spoofing is not supported.\n");
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return;
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}
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i = ixgbe_ethertype_filter_lookup(filter_info,
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IXGBE_ETHERTYPE_FLOW_CTRL);
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if (i >= 0) {
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PMD_DRV_LOG(ERR, "A ether type filter entity for flow control already exists!\n");
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return;
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}
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ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
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ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
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IXGBE_ETQF_TX_ANTISPOOF |
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IXGBE_ETHERTYPE_FLOW_CTRL;
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ethertype_filter.etqs = 0;
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ethertype_filter.conf = TRUE;
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i = ixgbe_ethertype_filter_insert(filter_info,
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ðertype_filter);
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if (i < 0) {
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PMD_DRV_LOG(ERR, "Cannot find an unused ether type filter entity for flow control.\n");
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return;
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}
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
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(IXGBE_ETQF_FILTER_EN |
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IXGBE_ETQF_TX_ANTISPOOF |
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IXGBE_ETHERTYPE_FLOW_CTRL));
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vf_num = dev_num_vf(eth_dev);
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for (i = 0; i < vf_num; i++)
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hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
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}
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int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
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{
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uint32_t vtctl, fcrth;
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uint32_t vfre_slot, vfre_offset;
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uint16_t vf_num;
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const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
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const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
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uint32_t gpie, gcr_ext;
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uint32_t vlanctrl;
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int i;
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vf_num = dev_num_vf(eth_dev);
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if (vf_num == 0)
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return -1;
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/* enable VMDq and set the default pool for PF */
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vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
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vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
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vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
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vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
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<< IXGBE_VT_CTL_POOL_SHIFT;
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vtctl |= IXGBE_VT_CTL_REPLEN;
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IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
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vfre_offset = vf_num & VFRE_MASK;
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vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
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/* Enable pools reserved to PF only */
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IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
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IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
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IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
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IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
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/* PFDMA Tx General Switch Control Enables VMDQ loopback */
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IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
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/* clear VMDq map to perment rar 0 */
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hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
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/* clear VMDq map to scan rar 127 */
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IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
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IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
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/* set VMDq map to default PF pool */
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hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
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/*
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* SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
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*/
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gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
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gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
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gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
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gpie &= ~IXGBE_GPIE_VTMODE_MASK;
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gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT;
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switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
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case ETH_64_POOLS:
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gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
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gpie |= IXGBE_GPIE_VTMODE_64;
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break;
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case ETH_32_POOLS:
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gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
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gpie |= IXGBE_GPIE_VTMODE_32;
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break;
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case ETH_16_POOLS:
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gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
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gpie |= IXGBE_GPIE_VTMODE_16;
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break;
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}
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IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
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IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
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/*
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* enable vlan filtering and allow all vlan tags through
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*/
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vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
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vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
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IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
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/* VFTA - enable all vlan filters */
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for (i = 0; i < IXGBE_MAX_VFTA; i++)
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IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
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/* Enable MAC Anti-Spoofing */
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hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
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/* set flow control threshold to max to avoid tx switch hang */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
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}
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ixgbe_add_tx_flow_control_drop_filter(eth_dev);
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return 0;
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}
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static void
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set_rx_mode(struct rte_eth_dev *dev)
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{
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struct rte_eth_dev_data *dev_data = dev->data;
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
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uint16_t vfn = dev_num_vf(dev);
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/* Check for Promiscuous and All Multicast modes */
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fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
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/* set all bits that we expect to always be set */
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fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
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fctrl |= IXGBE_FCTRL_BAM;
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/* clear the bits we are changing the status of */
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fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
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if (dev_data->promiscuous) {
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fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
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vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
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} else {
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if (dev_data->all_multicast) {
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fctrl |= IXGBE_FCTRL_MPE;
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vmolr |= IXGBE_VMOLR_MPE;
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} else {
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vmolr |= IXGBE_VMOLR_ROMPE;
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}
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}
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if (hw->mac.type != ixgbe_mac_82598EB) {
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vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
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~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
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IXGBE_VMOLR_ROPE);
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IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
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}
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IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
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ixgbe_vlan_hw_strip_config(dev);
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}
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static inline void
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ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
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{
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struct ixgbe_hw *hw =
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IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ixgbe_vf_info *vfinfo =
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*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
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int rar_entry = hw->mac.num_rar_entries - (vf + 1);
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uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
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vmolr |= (IXGBE_VMOLR_ROPE |
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IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
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IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
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IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
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/* reset multicast table array for vf */
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vfinfo[vf].num_vf_mc_hashes = 0;
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/* reset rx mode */
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set_rx_mode(dev);
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hw->mac.ops.clear_rar(hw, rar_entry);
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}
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static inline void
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ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t reg;
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uint32_t reg_offset, vf_shift;
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const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
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const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
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uint8_t nb_q_per_pool;
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int i;
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vf_shift = vf & VFRE_MASK;
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reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
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/* enable transmit for vf */
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reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
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reg |= (reg | (1 << vf_shift));
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IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
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/* enable all queue drop for IOV */
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nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
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for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) {
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IXGBE_WRITE_FLUSH(hw);
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reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE;
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reg |= i << IXGBE_QDE_IDX_SHIFT;
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IXGBE_WRITE_REG(hw, IXGBE_QDE, reg);
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}
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/* enable receive for vf */
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reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
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reg |= (reg | (1 << vf_shift));
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IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
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/* Enable counting of spoofed packets in the SSVPC register */
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reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
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reg |= (1 << vf_shift);
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IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
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ixgbe_vf_reset_event(dev, vf);
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}
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static int
|
|
ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
|
|
{
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
uint32_t vmolr;
|
|
|
|
vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
|
|
|
|
PMD_DRV_LOG(INFO, "VF %u: disabling multicast promiscuous\n", vf);
|
|
|
|
vmolr &= ~IXGBE_VMOLR_MPE;
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
|
|
unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
|
|
int rar_entry = hw->mac.num_rar_entries - (vf + 1);
|
|
uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
|
|
|
|
ixgbe_vf_reset_msg(dev, vf);
|
|
|
|
hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
|
|
|
|
/* Disable multicast promiscuous at reset */
|
|
ixgbe_disable_vf_mc_promisc(dev, vf);
|
|
|
|
/* reply to reset with ack and vf mac address */
|
|
msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
|
|
rte_memcpy(new_mac, vf_mac, RTE_ETHER_ADDR_LEN);
|
|
/*
|
|
* Piggyback the multicast filter type so VF can compute the
|
|
* correct vectors
|
|
*/
|
|
msgbuf[3] = hw->mac.mc_filter_type;
|
|
ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
|
|
int rar_entry = hw->mac.num_rar_entries - (vf + 1);
|
|
uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
|
|
|
|
if (rte_is_valid_assigned_ether_addr(
|
|
(struct rte_ether_addr *)new_mac)) {
|
|
rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
|
|
return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
|
|
int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
|
|
IXGBE_VT_MSGINFO_SHIFT;
|
|
uint16_t *hash_list = (uint16_t *)&msgbuf[1];
|
|
uint32_t mta_idx;
|
|
uint32_t mta_shift;
|
|
const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
|
|
const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
|
|
const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
|
|
uint32_t reg_val;
|
|
int i;
|
|
u32 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
|
|
|
|
/* Disable multicast promiscuous first */
|
|
ixgbe_disable_vf_mc_promisc(dev, vf);
|
|
|
|
/* only so many hash values supported */
|
|
nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
|
|
|
|
/* store the mc entries */
|
|
vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
|
|
for (i = 0; i < nb_entries; i++) {
|
|
vfinfo->vf_mc_hashes[i] = hash_list[i];
|
|
}
|
|
|
|
if (nb_entries == 0) {
|
|
vmolr &= ~IXGBE_VMOLR_ROMPE;
|
|
IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
|
|
mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
|
|
& IXGBE_MTA_INDEX_MASK;
|
|
mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
|
|
reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
|
|
reg_val |= (1 << mta_shift);
|
|
IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
|
|
}
|
|
|
|
vmolr |= IXGBE_VMOLR_ROMPE;
|
|
IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
int add, vid;
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
|
|
|
|
add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
|
|
>> IXGBE_VT_MSGINFO_SHIFT;
|
|
vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
|
|
|
|
if (add)
|
|
vfinfo[vf].vlan_count++;
|
|
else if (vfinfo[vf].vlan_count)
|
|
vfinfo[vf].vlan_count--;
|
|
return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
|
|
}
|
|
|
|
static int
|
|
ixgbe_set_vf_lpe(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
uint32_t max_frame = msgbuf[1];
|
|
uint32_t max_frs;
|
|
uint32_t hlreg0;
|
|
|
|
/* X540 and X550 support jumbo frames in IOV mode */
|
|
if (hw->mac.type != ixgbe_mac_X540 &&
|
|
hw->mac.type != ixgbe_mac_X550 &&
|
|
hw->mac.type != ixgbe_mac_X550EM_x &&
|
|
hw->mac.type != ixgbe_mac_X550EM_a) {
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
|
|
|
|
switch (vfinfo[vf].api_version) {
|
|
case ixgbe_mbox_api_11:
|
|
case ixgbe_mbox_api_12:
|
|
case ixgbe_mbox_api_13:
|
|
/**
|
|
* Version 1.1&1.2&1.3 supports jumbo frames on VFs
|
|
* if PF has jumbo frames enabled which means legacy
|
|
* VFs are disabled.
|
|
*/
|
|
if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
|
|
IXGBE_ETH_MAX_LEN)
|
|
break;
|
|
/* fall through */
|
|
default:
|
|
/**
|
|
* If the PF or VF are running w/ jumbo frames enabled,
|
|
* we return -1 as we cannot support jumbo frames on
|
|
* legacy VFs.
|
|
*/
|
|
if (max_frame > IXGBE_ETH_MAX_LEN ||
|
|
dev->data->dev_conf.rxmode.max_rx_pkt_len >
|
|
IXGBE_ETH_MAX_LEN)
|
|
return -1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (max_frame < RTE_ETHER_MIN_LEN ||
|
|
max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
|
|
return -1;
|
|
|
|
max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
|
|
IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
|
|
if (max_frs < max_frame) {
|
|
hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
|
|
if (max_frame > IXGBE_ETH_MAX_LEN) {
|
|
dev->data->dev_conf.rxmode.offloads |=
|
|
DEV_RX_OFFLOAD_JUMBO_FRAME;
|
|
hlreg0 |= IXGBE_HLREG0_JUMBOEN;
|
|
} else {
|
|
dev->data->dev_conf.rxmode.offloads &=
|
|
~DEV_RX_OFFLOAD_JUMBO_FRAME;
|
|
hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
|
|
}
|
|
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
|
|
|
|
max_frs = max_frame << IXGBE_MHADD_MFS_SHIFT;
|
|
IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
uint32_t api_version = msgbuf[1];
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
|
|
|
|
switch (api_version) {
|
|
case ixgbe_mbox_api_10:
|
|
case ixgbe_mbox_api_11:
|
|
case ixgbe_mbox_api_12:
|
|
case ixgbe_mbox_api_13:
|
|
vfinfo[vf].api_version = (uint8_t)api_version;
|
|
return 0;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
PMD_DRV_LOG(ERR, "Negotiate invalid api version %u from VF %d\n",
|
|
api_version, vf);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
|
|
uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
|
|
struct rte_eth_conf *eth_conf;
|
|
struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf;
|
|
u8 num_tcs;
|
|
struct ixgbe_hw *hw;
|
|
u32 vmvir;
|
|
#define IXGBE_VMVIR_VLANA_MASK 0xC0000000
|
|
#define IXGBE_VMVIR_VLAN_VID_MASK 0x00000FFF
|
|
#define IXGBE_VMVIR_VLAN_UP_MASK 0x0000E000
|
|
#define VLAN_PRIO_SHIFT 13
|
|
u32 vlana;
|
|
u32 vid;
|
|
u32 user_priority;
|
|
|
|
/* Verify if the PF supports the mbox APIs version or not */
|
|
switch (vfinfo[vf].api_version) {
|
|
case ixgbe_mbox_api_20:
|
|
case ixgbe_mbox_api_11:
|
|
case ixgbe_mbox_api_12:
|
|
case ixgbe_mbox_api_13:
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
/* Notify VF of Rx and Tx queue number */
|
|
msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
|
|
msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
|
|
|
|
/* Notify VF of default queue */
|
|
msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
|
|
|
|
/* Notify VF of number of DCB traffic classes */
|
|
eth_conf = &dev->data->dev_conf;
|
|
switch (eth_conf->txmode.mq_mode) {
|
|
case ETH_MQ_TX_NONE:
|
|
case ETH_MQ_TX_DCB:
|
|
PMD_DRV_LOG(ERR, "PF must work with virtualization for VF %u"
|
|
", but its tx mode = %d\n", vf,
|
|
eth_conf->txmode.mq_mode);
|
|
return -1;
|
|
|
|
case ETH_MQ_TX_VMDQ_DCB:
|
|
vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf;
|
|
switch (vmdq_dcb_tx_conf->nb_queue_pools) {
|
|
case ETH_16_POOLS:
|
|
num_tcs = ETH_8_TCS;
|
|
break;
|
|
case ETH_32_POOLS:
|
|
num_tcs = ETH_4_TCS;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
break;
|
|
|
|
/* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */
|
|
case ETH_MQ_TX_VMDQ_ONLY:
|
|
hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
|
|
vlana = vmvir & IXGBE_VMVIR_VLANA_MASK;
|
|
vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK;
|
|
user_priority =
|
|
(vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT;
|
|
if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) &&
|
|
((vid != 0) || (user_priority != 0)))
|
|
num_tcs = 1;
|
|
else
|
|
num_tcs = 0;
|
|
break;
|
|
|
|
default:
|
|
PMD_DRV_LOG(ERR, "PF work with invalid mode = %d\n",
|
|
eth_conf->txmode.mq_mode);
|
|
return -1;
|
|
}
|
|
msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
int xcast_mode = msgbuf[1]; /* msgbuf contains the flag to enable */
|
|
u32 vmolr, fctrl, disable, enable;
|
|
|
|
switch (vfinfo[vf].api_version) {
|
|
case ixgbe_mbox_api_12:
|
|
/* promisc introduced in 1.3 version */
|
|
if (xcast_mode == IXGBEVF_XCAST_MODE_PROMISC)
|
|
return -EOPNOTSUPP;
|
|
break;
|
|
/* Fall threw */
|
|
case ixgbe_mbox_api_13:
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
if (vfinfo[vf].xcast_mode == xcast_mode)
|
|
goto out;
|
|
|
|
switch (xcast_mode) {
|
|
case IXGBEVF_XCAST_MODE_NONE:
|
|
disable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
|
|
IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
|
|
enable = 0;
|
|
break;
|
|
case IXGBEVF_XCAST_MODE_MULTI:
|
|
disable = IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
|
|
enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE;
|
|
break;
|
|
case IXGBEVF_XCAST_MODE_ALLMULTI:
|
|
disable = IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
|
|
enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_MPE;
|
|
break;
|
|
case IXGBEVF_XCAST_MODE_PROMISC:
|
|
if (hw->mac.type <= ixgbe_mac_82599EB)
|
|
return -1;
|
|
|
|
fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
|
|
if (!(fctrl & IXGBE_FCTRL_UPE)) {
|
|
/* VF promisc requires PF in promisc */
|
|
PMD_DRV_LOG(ERR,
|
|
"Enabling VF promisc requires PF in promisc\n");
|
|
return -1;
|
|
}
|
|
|
|
disable = 0;
|
|
enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
|
|
IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
|
|
vmolr &= ~disable;
|
|
vmolr |= enable;
|
|
IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
|
|
vfinfo[vf].xcast_mode = xcast_mode;
|
|
|
|
out:
|
|
msgbuf[1] = xcast_mode;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_set_vf_macvlan_msg(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
|
|
{
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vf_info =
|
|
*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
|
|
uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
|
|
int index = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
|
|
IXGBE_VT_MSGINFO_SHIFT;
|
|
|
|
if (index) {
|
|
if (!rte_is_valid_assigned_ether_addr(
|
|
(struct rte_ether_addr *)new_mac)) {
|
|
PMD_DRV_LOG(ERR, "set invalid mac vf:%d\n", vf);
|
|
return -1;
|
|
}
|
|
|
|
vf_info[vf].mac_count++;
|
|
|
|
hw->mac.ops.set_rar(hw, vf_info[vf].mac_count,
|
|
new_mac, vf, IXGBE_RAH_AV);
|
|
} else {
|
|
if (vf_info[vf].mac_count) {
|
|
hw->mac.ops.clear_rar(hw, vf_info[vf].mac_count);
|
|
vf_info[vf].mac_count = 0;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
|
|
{
|
|
uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
|
|
uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
|
|
uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
|
|
int32_t retval;
|
|
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
|
|
struct rte_pmd_ixgbe_mb_event_param ret_param;
|
|
|
|
retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
|
|
if (retval) {
|
|
PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
|
|
return retval;
|
|
}
|
|
|
|
/* do nothing with the message already been processed */
|
|
if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
|
|
return retval;
|
|
|
|
/* flush the ack before we write any messages back */
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
/**
|
|
* initialise structure to send to user application
|
|
* will return response from user in retval field
|
|
*/
|
|
ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
|
|
ret_param.vfid = vf;
|
|
ret_param.msg_type = msgbuf[0] & 0xFFFF;
|
|
ret_param.msg = (void *)msgbuf;
|
|
|
|
/* perform VF reset */
|
|
if (msgbuf[0] == IXGBE_VF_RESET) {
|
|
int ret = ixgbe_vf_reset(dev, vf, msgbuf);
|
|
|
|
vfinfo[vf].clear_to_send = true;
|
|
|
|
/* notify application about VF reset */
|
|
rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
|
|
&ret_param);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ask user application if we allowed to perform those functions
|
|
* if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
|
|
* then business as usual,
|
|
* if 0, do nothing and send ACK to VF
|
|
* if ret_param.retval > 1, do nothing and send NAK to VF
|
|
*/
|
|
rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &ret_param);
|
|
|
|
retval = ret_param.retval;
|
|
|
|
/* check & process VF to PF mailbox message */
|
|
switch ((msgbuf[0] & 0xFFFF)) {
|
|
case IXGBE_VF_SET_MAC_ADDR:
|
|
if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
|
|
retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
|
|
break;
|
|
case IXGBE_VF_SET_MULTICAST:
|
|
if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
|
|
retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
|
|
break;
|
|
case IXGBE_VF_SET_LPE:
|
|
if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
|
|
retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
|
|
break;
|
|
case IXGBE_VF_SET_VLAN:
|
|
if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
|
|
retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
|
|
break;
|
|
case IXGBE_VF_API_NEGOTIATE:
|
|
retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
|
|
break;
|
|
case IXGBE_VF_GET_QUEUES:
|
|
retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
|
|
msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
|
|
break;
|
|
case IXGBE_VF_UPDATE_XCAST_MODE:
|
|
if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
|
|
retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
|
|
break;
|
|
case IXGBE_VF_SET_MACVLAN:
|
|
if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
|
|
retval = ixgbe_set_vf_macvlan_msg(dev, vf, msgbuf);
|
|
break;
|
|
default:
|
|
PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
|
|
retval = IXGBE_ERR_MBX;
|
|
break;
|
|
}
|
|
|
|
/* response the VF according to the message process result */
|
|
if (retval)
|
|
msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
|
|
else
|
|
msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
|
|
|
|
msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
|
|
|
|
ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static inline void
|
|
ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
|
|
{
|
|
uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
|
|
struct ixgbe_hw *hw =
|
|
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
struct ixgbe_vf_info *vfinfo =
|
|
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
|
|
|
|
if (!vfinfo[vf].clear_to_send)
|
|
ixgbe_write_mbx(hw, &msg, 1, vf);
|
|
}
|
|
|
|
void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
|
|
{
|
|
uint16_t vf;
|
|
struct ixgbe_hw *hw =
|
|
IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
|
|
|
|
for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
|
|
/* check & process vf function level reset */
|
|
if (!ixgbe_check_for_rst(hw, vf))
|
|
ixgbe_vf_reset_event(eth_dev, vf);
|
|
|
|
/* check & process vf mailbox messages */
|
|
if (!ixgbe_check_for_msg(hw, vf))
|
|
ixgbe_rcv_msg_from_vf(eth_dev, vf);
|
|
|
|
/* check & process acks from vf */
|
|
if (!ixgbe_check_for_ack(hw, vf))
|
|
ixgbe_rcv_ack_from_vf(eth_dev, vf);
|
|
}
|
|
}
|