87e1160c2c
Add locking for IPsec table updates. Fixed error handling to clear SA entry if the SA population functions encounters any error. Signed-off-by: Anoob Joseph <anoobj@marvell.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
621 lines
20 KiB
C
621 lines
20 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_ETHDEV_H__
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#define __OTX2_ETHDEV_H__
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#include <math.h>
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#include <stdint.h>
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#include <rte_common.h>
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#include <rte_ethdev.h>
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#include <rte_kvargs.h>
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include <rte_security_driver.h>
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#include <rte_spinlock.h>
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#include <rte_string_fns.h>
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#include <rte_time.h>
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#include "otx2_common.h"
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#include "otx2_dev.h"
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#include "otx2_flow.h"
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#include "otx2_irq.h"
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#include "otx2_mempool.h"
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#include "otx2_rx.h"
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#include "otx2_tm.h"
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#include "otx2_tx.h"
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#define OTX2_ETH_DEV_PMD_VERSION "1.0"
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/* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
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/* Minimum CQ size should be 4K */
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#define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
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#define otx2_ethdev_fixup_is_min_4k_q(dev) \
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((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
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/* Limit CQ being full */
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#define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
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#define otx2_ethdev_fixup_is_limit_cq_full(dev) \
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((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
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/* Used for struct otx2_eth_dev::flags */
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#define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
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/* VLAN tag inserted by NIX_TX_VTAG_ACTION.
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* In Tx space is always reserved for this in FRS.
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*/
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#define NIX_MAX_VTAG_INS 2
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#define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
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/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
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#define NIX_L2_OVERHEAD \
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(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
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#define NIX_L2_MAX_LEN \
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(RTE_ETHER_MTU + NIX_L2_OVERHEAD)
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/* HW config of frame size doesn't include FCS */
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#define NIX_MAX_HW_FRS 9212
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#define NIX_MIN_HW_FRS 60
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/* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
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#define NIX_MAX_FRS \
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(NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
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#define NIX_MIN_FRS \
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(NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
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#define NIX_MAX_MTU \
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(NIX_MAX_FRS - NIX_L2_OVERHEAD)
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#define NIX_MAX_SQB 512
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#define NIX_DEF_SQB 16
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#define NIX_MIN_SQB 8
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#define NIX_SQB_LIST_SPACE 2
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#define NIX_RSS_RETA_SIZE_MAX 256
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/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
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#define NIX_RSS_GRPS 8
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#define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
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#define NIX_RSS_RETA_SIZE 64
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#define NIX_RX_MIN_DESC 16
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#define NIX_RX_MIN_DESC_ALIGN 16
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#define NIX_RX_NB_SEG_MAX 6
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#define NIX_CQ_ENTRY_SZ 128
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#define NIX_CQ_ALIGN 512
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#define NIX_SQB_LOWER_THRESH 70
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#define LMT_SLOT_MASK 0x7f
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#define NIX_RX_DEFAULT_RING_SZ 4096
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/* If PTP is enabled additional SEND MEM DESC is required which
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* takes 2 words, hence max 7 iova address are possible
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*/
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#if defined(RTE_LIBRTE_IEEE1588)
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#define NIX_TX_NB_SEG_MAX 7
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#else
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#define NIX_TX_NB_SEG_MAX 9
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#endif
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#define NIX_TX_MSEG_SG_DWORDS \
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((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
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+ NIX_TX_NB_SEG_MAX)
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/* Apply BP/DROP when CQ is 95% full */
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#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
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#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
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#define CQ_OP_STAT_OP_ERR 63
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#define CQ_OP_STAT_CQ_ERR 46
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#define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
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#define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
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#define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
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* NIX_LF_CINTX_CNT[QCOUNT]
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* crosses this value
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*/
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#define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
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#define CQ_TIMER_THRESH_MAX 255
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#define NIX_RSS_L3_L4_SRC_DST (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY \
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| ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)
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#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
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ETH_RSS_TCP | ETH_RSS_SCTP | \
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ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
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NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | \
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ETH_RSS_C_VLAN)
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#define NIX_TX_OFFLOAD_CAPA ( \
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DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
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DEV_TX_OFFLOAD_MT_LOCKFREE | \
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DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_QINQ_INSERT | \
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
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DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
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DEV_TX_OFFLOAD_GRE_TNL_TSO | \
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DEV_TX_OFFLOAD_MULTI_SEGS | \
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DEV_TX_OFFLOAD_IPV4_CKSUM)
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#define NIX_RX_OFFLOAD_CAPA ( \
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DEV_RX_OFFLOAD_CHECKSUM | \
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DEV_RX_OFFLOAD_SCTP_CKSUM | \
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DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
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DEV_RX_OFFLOAD_SCATTER | \
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DEV_RX_OFFLOAD_JUMBO_FRAME | \
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DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_RX_OFFLOAD_VLAN_STRIP | \
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DEV_RX_OFFLOAD_VLAN_FILTER | \
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DEV_RX_OFFLOAD_QINQ_STRIP | \
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DEV_RX_OFFLOAD_TIMESTAMP | \
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DEV_RX_OFFLOAD_RSS_HASH)
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#define NIX_DEFAULT_RSS_CTX_GROUP 0
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#define NIX_DEFAULT_RSS_MCAM_IDX -1
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#define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
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#define NIX_TIMESYNC_TX_CMD_LEN 8
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/* Additional timesync values. */
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#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
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#define OCTEONTX2_PMD net_octeontx2
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#define otx2_ethdev_is_same_driver(dev) \
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(strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
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enum nix_q_size_e {
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nix_q_size_16, /* 16 entries */
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nix_q_size_64, /* 64 entries */
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nix_q_size_256,
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nix_q_size_1K,
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nix_q_size_4K,
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nix_q_size_16K,
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nix_q_size_64K,
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nix_q_size_256K,
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nix_q_size_1M, /* Million entries */
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nix_q_size_max
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};
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enum nix_lso_tun_type {
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NIX_LSO_TUN_V4V4,
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NIX_LSO_TUN_V4V6,
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NIX_LSO_TUN_V6V4,
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NIX_LSO_TUN_V6V6,
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NIX_LSO_TUN_MAX,
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};
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struct otx2_qint {
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struct rte_eth_dev *eth_dev;
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uint8_t qintx;
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};
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struct otx2_rss_info {
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uint64_t nix_rss;
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uint32_t flowkey_cfg;
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uint16_t rss_size;
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uint8_t rss_grps;
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uint8_t alg_idx; /* Selected algo index */
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uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
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uint8_t key[NIX_HASH_KEY_SIZE];
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};
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struct otx2_eth_qconf {
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union {
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struct rte_eth_txconf tx;
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struct rte_eth_rxconf rx;
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} conf;
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void *mempool;
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uint32_t socket_id;
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uint16_t nb_desc;
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uint8_t valid;
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};
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struct otx2_fc_info {
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enum rte_eth_fc_mode mode; /**< Link flow control mode */
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uint8_t rx_pause;
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uint8_t tx_pause;
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uint8_t chan_cnt;
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uint16_t bpid[NIX_MAX_CHAN];
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};
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struct vlan_mkex_info {
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struct npc_xtract_info la_xtract;
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struct npc_xtract_info lb_xtract;
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uint64_t lb_lt_offset;
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};
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struct mcast_entry {
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struct rte_ether_addr mcast_mac;
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uint16_t mcam_index;
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TAILQ_ENTRY(mcast_entry) next;
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};
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TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);
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struct vlan_entry {
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uint32_t mcam_idx;
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uint16_t vlan_id;
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TAILQ_ENTRY(vlan_entry) next;
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};
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TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
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struct otx2_vlan_info {
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struct otx2_vlan_filter_tbl fltr_tbl;
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/* MKEX layer info */
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struct mcam_entry def_tx_mcam_ent;
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struct mcam_entry def_rx_mcam_ent;
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struct vlan_mkex_info mkex;
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/* Default mcam entry that matches vlan packets */
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uint32_t def_rx_mcam_idx;
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uint32_t def_tx_mcam_idx;
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/* MCAM entry that matches double vlan packets */
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uint32_t qinq_mcam_idx;
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/* Indices of tx_vtag def registers */
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uint32_t outer_vlan_idx;
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uint32_t inner_vlan_idx;
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uint16_t outer_vlan_tpid;
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uint16_t inner_vlan_tpid;
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uint16_t pvid;
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/* QinQ entry allocated before default one */
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uint8_t qinq_before_def;
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uint8_t pvid_insert_on;
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/* Rx vtag action type */
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uint8_t vtag_type_idx;
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uint8_t filter_on;
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uint8_t strip_on;
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uint8_t qinq_on;
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uint8_t promisc_on;
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};
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struct otx2_eth_dev {
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OTX2_DEV; /* Base class */
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RTE_MARKER otx2_eth_dev_data_start;
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uint16_t sqb_size;
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uint16_t rx_chan_base;
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uint16_t tx_chan_base;
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uint8_t rx_chan_cnt;
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uint8_t tx_chan_cnt;
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uint8_t lso_tsov4_idx;
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uint8_t lso_tsov6_idx;
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uint8_t lso_udp_tun_idx[NIX_LSO_TUN_MAX];
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uint8_t lso_tun_idx[NIX_LSO_TUN_MAX];
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uint64_t lso_tun_fmt;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t mkex_pfl_name[MKEX_NAME_LEN];
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uint8_t max_mac_entries;
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bool dmac_filter_enable;
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uint8_t lf_tx_stats;
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uint8_t lf_rx_stats;
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uint8_t lock_rx_ctx;
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uint8_t lock_tx_ctx;
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uint16_t flags;
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uint16_t cints;
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uint16_t qints;
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uint8_t configured;
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uint8_t configured_qints;
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uint8_t configured_cints;
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uint8_t configured_nb_rx_qs;
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uint8_t configured_nb_tx_qs;
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uint8_t ptype_disable;
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uint16_t nix_msixoff;
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uintptr_t base;
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uintptr_t lmt_addr;
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uint16_t scalar_ena;
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uint16_t rss_tag_as_xor;
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uint16_t max_sqb_count;
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uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
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uint64_t rx_offloads;
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uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
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uint64_t tx_offloads;
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uint64_t rx_offload_capa;
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uint64_t tx_offload_capa;
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struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
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struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
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uint16_t txschq[NIX_TXSCH_LVL_CNT];
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uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
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uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
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uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
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/* Dis-contiguous queues */
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uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
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/* Contiguous queues */
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uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
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uint16_t otx2_tm_root_lvl;
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uint16_t link_cfg_lvl;
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uint16_t tm_flags;
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uint16_t tm_leaf_cnt;
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uint64_t tm_rate_min;
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struct otx2_nix_tm_node_list node_list;
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struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
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struct otx2_rss_info rss_info;
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struct otx2_fc_info fc_info;
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uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
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uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
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struct otx2_npc_flow_info npc_flow;
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struct otx2_vlan_info vlan_info;
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struct otx2_eth_qconf *tx_qconf;
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struct otx2_eth_qconf *rx_qconf;
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struct rte_eth_dev *eth_dev;
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eth_rx_burst_t rx_pkt_burst_no_offload;
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/* PTP counters */
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bool ptp_en;
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struct otx2_timesync_info tstamp;
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struct rte_timecounter systime_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct rte_timecounter tx_tstamp_tc;
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double clk_freq_mult;
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uint64_t clk_delta;
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bool mc_tbl_set;
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struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
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bool sdp_link; /* SDP flag */
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/* Inline IPsec params */
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uint16_t ipsec_in_max_spi;
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rte_spinlock_t ipsec_tbl_lock;
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uint8_t duplex;
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uint32_t speed;
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} __rte_cache_aligned;
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struct otx2_eth_txq {
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uint64_t cmd[8];
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int64_t fc_cache_pkts;
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uint64_t *fc_mem;
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void *lmt_addr;
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rte_iova_t io_addr;
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rte_iova_t fc_iova;
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uint16_t sqes_per_sqb_log2;
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int16_t nb_sqb_bufs_adj;
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uint64_t lso_tun_fmt;
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RTE_MARKER slow_path_start;
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uint16_t nb_sqb_bufs;
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uint16_t sq;
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uint64_t offloads;
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struct otx2_eth_dev *dev;
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struct rte_mempool *sqb_pool;
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struct otx2_eth_qconf qconf;
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} __rte_cache_aligned;
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struct otx2_eth_rxq {
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uint64_t mbuf_initializer;
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uint64_t data_off;
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uintptr_t desc;
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void *lookup_mem;
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uintptr_t cq_door;
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uint64_t wdata;
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int64_t *cq_status;
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uint32_t head;
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uint32_t qmask;
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uint32_t available;
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uint16_t rq;
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struct otx2_timesync_info *tstamp;
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RTE_MARKER slow_path_start;
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uint64_t aura;
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uint64_t offloads;
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uint32_t qlen;
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struct rte_mempool *pool;
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enum nix_q_size_e qsize;
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struct rte_eth_dev *eth_dev;
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struct otx2_eth_qconf qconf;
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uint16_t cq_drop;
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} __rte_cache_aligned;
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static inline struct otx2_eth_dev *
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otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
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{
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return eth_dev->data->dev_private;
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}
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/* Ops */
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int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_dev_info *dev_info);
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int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,
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const struct rte_flow_ops **ops);
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int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
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size_t fw_size);
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int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
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struct rte_eth_dev_module_info *modinfo);
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int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
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struct rte_dev_eeprom_info *info);
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int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
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void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
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struct rte_eth_rxq_info *qinfo);
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void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
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struct rte_eth_txq_info *qinfo);
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int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_burst_mode *mode);
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int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_burst_mode *mode);
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uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
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int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
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int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
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int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
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int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);
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void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
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int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
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int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
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int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
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int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
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int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
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int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
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uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
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/* Multicast filter APIs */
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void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);
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void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);
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int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);
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int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);
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int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
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struct rte_ether_addr *mc_addr_set,
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uint32_t nb_mc_addr);
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/* MTU */
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int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
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int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
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void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
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/* Link */
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void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
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int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
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void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
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struct cgx_link_user_info *link);
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void otx2_eth_dev_link_status_get(struct otx2_dev *dev,
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struct cgx_link_user_info *link);
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int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
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int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
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int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
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/* IRQ */
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int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
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int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
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int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
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void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
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void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
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void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
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void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
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void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
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int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
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uint16_t rx_queue_id);
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int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
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uint16_t rx_queue_id);
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/* Debug */
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int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
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int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
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struct rte_dev_reg_info *regs);
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int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
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void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
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void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
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/* Stats */
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int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_stats *stats);
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int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
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int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
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uint16_t queue_id, uint8_t stat_idx,
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uint8_t is_rx);
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int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_xstat *xstats, unsigned int n);
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int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
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struct rte_eth_xstat_name *xstats_names,
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unsigned int limit);
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int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
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int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
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const uint64_t *ids,
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uint64_t *values, unsigned int n);
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int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
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struct rte_eth_xstat_name *xstats_names,
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const uint64_t *ids, unsigned int limit);
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/* RSS */
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void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
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uint8_t *key, uint32_t key_len);
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uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
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uint64_t ethdev_rss, uint8_t rss_level);
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int otx2_rss_set_hf(struct otx2_eth_dev *dev,
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uint32_t flowkey_cfg, uint8_t *alg_idx,
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uint8_t group, int mcam_index);
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int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
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uint16_t *ind_tbl);
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int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
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int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf);
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int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf);
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/* CGX */
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int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
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int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
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int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
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struct rte_ether_addr *addr);
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/* Flow Control */
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int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
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int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_fc_conf *fc_conf);
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|
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int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
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struct rte_eth_fc_conf *fc_conf);
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|
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int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
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int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
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|
|
|
/* VLAN */
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|
int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
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|
int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
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|
int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
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|
void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
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|
int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
|
|
int on);
|
|
void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
|
|
uint16_t queue, int on);
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|
int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
|
|
enum rte_vlan_type type, uint16_t tpid);
|
|
int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
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|
|
|
/* Lookup configuration */
|
|
void *otx2_nix_fastpath_lookup_mem_get(void);
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|
|
|
/* PTYPES */
|
|
const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
|
|
int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);
|
|
|
|
/* Mac address handling */
|
|
int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
|
|
struct rte_ether_addr *addr);
|
|
int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
|
|
int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
|
|
struct rte_ether_addr *addr,
|
|
uint32_t index, uint32_t pool);
|
|
void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
|
|
int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
|
|
|
|
/* Devargs */
|
|
int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
|
|
struct otx2_eth_dev *dev);
|
|
|
|
/* Rx and Tx routines */
|
|
void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
|
|
void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
|
|
void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
|
|
|
|
/* Timesync - PTP routines */
|
|
int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
|
|
int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
|
|
int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
|
|
struct timespec *timestamp,
|
|
uint32_t flags);
|
|
int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
|
|
struct timespec *timestamp);
|
|
int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
|
|
int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
|
|
const struct timespec *ts);
|
|
int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
|
|
struct timespec *ts);
|
|
int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
|
|
int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
|
|
int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
|
|
void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
|
|
|
|
#endif /* __OTX2_ETHDEV_H__ */
|