046f116195
Add support for MSI-X interrupt vectors to the vmxnet3 driver. This will allow more efficient deployments in cloud environments. By default it will try to allocate 1 vector (0) for link event and one MSI-X vector for each Rx queue. To simplify things, it will only be enabled if the number of Tx and Rx queues are equal (so that Tx/Rx share the same vector). If for any reason vmxnet3 cannot enable intr mode, it will fall back to the LSC only mode. Signed-off-by: Yong Wang <yongwang@vmware.com> Signed-off-by: Jochen Behrens <jbehrens@vmware.com>
221 lines
6.8 KiB
C
221 lines
6.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2014 Intel Corporation
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*/
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#ifndef _VMXNET3_ETHDEV_H_
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#define _VMXNET3_ETHDEV_H_
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#include <rte_io.h>
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#include <rte_mbuf_dyn.h>
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#define VMXNET3_MAX_MAC_ADDRS 1
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/* UPT feature to negotiate */
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#define VMXNET3_F_RXCSUM 0x0001
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#define VMXNET3_F_RSS 0x0002
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#define VMXNET3_F_RXVLAN 0x0004
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#define VMXNET3_F_LRO 0x0008
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/* Hash Types supported by device */
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#define VMXNET3_RSS_HASH_TYPE_NONE 0x0
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#define VMXNET3_RSS_HASH_TYPE_IPV4 0x01
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#define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02
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#define VMXNET3_RSS_HASH_TYPE_IPV6 0x04
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#define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08
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#define VMXNET3_RSS_HASH_FUNC_NONE 0x0
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#define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01
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#define VMXNET3_RSS_MAX_KEY_SIZE 40
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#define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128
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#define VMXNET3_MAX_MSIX_VECT (VMXNET3_MAX_TX_QUEUES + \
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VMXNET3_MAX_RX_QUEUES + 1)
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#define VMXNET3_RSS_OFFLOAD_ALL ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP)
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#define VMXNET3_V4_RSS_MASK ( \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_NONFRAG_IPV6_UDP)
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#define VMXNET3_MANDATORY_V4_RSS ( \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV6_TCP)
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/* RSS configuration structure - shared with device through GPA */
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typedef struct VMXNET3_RSSConf {
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uint16_t hashType;
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uint16_t hashFunc;
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uint16_t hashKeySize;
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uint16_t indTableSize;
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uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
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/*
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* indTable is only element that can be changed without
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* device quiesce-reset-update-activation cycle
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*/
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uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
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} VMXNET3_RSSConf;
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typedef struct vmxnet3_mf_table {
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void *mfTableBase; /* Multicast addresses list */
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uint64_t mfTablePA; /* Physical address of the list */
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uint16_t num_addrs; /* number of multicast addrs */
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} vmxnet3_mf_table_t;
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struct vmxnet3_intr {
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enum vmxnet3_intr_mask_mode mask_mode;
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enum vmxnet3_intr_type type; /* MSI-X, MSI, or INTx? */
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uint8_t num_intrs; /* # of intr vectors */
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uint8_t event_intr_idx; /* idx of the intr vector for event */
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uint8_t mod_levels[VMXNET3_MAX_MSIX_VECT]; /* moderation level */
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bool lsc_only; /* no Rx queue interrupt */
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};
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struct vmxnet3_hw {
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uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */
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uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */
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/* BAR2: MSI-X Regs */
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/* BAR3: Port IO */
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void *back;
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uint16_t device_id;
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uint16_t vendor_id;
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uint16_t subsystem_device_id;
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uint16_t subsystem_vendor_id;
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bool adapter_stopped;
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uint8_t perm_addr[RTE_ETHER_ADDR_LEN];
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uint8_t num_tx_queues;
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uint8_t num_rx_queues;
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uint8_t bufs_per_pkt;
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uint8_t version;
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uint16_t txdata_desc_size; /* tx data ring buffer size */
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uint16_t rxdata_desc_size; /* rx data ring buffer size */
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uint8_t num_intrs;
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Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */
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Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */
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Vmxnet3_DriverShared *shared;
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uint64_t sharedPA;
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uint64_t queueDescPA;
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uint16_t queue_desc_len;
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uint16_t mtu;
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VMXNET3_RSSConf *rss_conf;
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uint64_t rss_confPA;
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vmxnet3_mf_table_t *mf_table;
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uint32_t shadow_vfta[VMXNET3_VFT_SIZE];
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struct vmxnet3_intr intr;
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Vmxnet3_MemRegs *memRegs;
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uint64_t memRegsPA;
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#define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t))
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UPT1_TxStats saved_tx_stats[VMXNET3_MAX_TX_QUEUES];
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UPT1_RxStats saved_rx_stats[VMXNET3_MAX_RX_QUEUES];
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UPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];
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UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];
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};
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#define VMXNET3_REV_4 3 /* Vmxnet3 Rev. 4 */
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#define VMXNET3_REV_3 2 /* Vmxnet3 Rev. 3 */
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#define VMXNET3_REV_2 1 /* Vmxnet3 Rev. 2 */
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#define VMXNET3_REV_1 0 /* Vmxnet3 Rev. 1 */
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#define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)
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#define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)
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#define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1)
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#define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))
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#define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))
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/* Config space read/writes */
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#define VMXNET3_PCI_REG(reg) rte_read32(reg)
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static inline uint32_t
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vmxnet3_read_addr(volatile void *addr)
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{
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return VMXNET3_PCI_REG(addr);
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}
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#define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
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#define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
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#define VMXNET3_READ_BAR0_REG(hw, reg) \
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vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
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#define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
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VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
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#define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
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#define VMXNET3_READ_BAR1_REG(hw, reg) \
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vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
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#define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
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VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
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static inline uint8_t
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vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID)
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{
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return (rqID >= hw->num_rx_queues &&
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rqID < 2 * hw->num_rx_queues) ? 1 : 0;
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}
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static inline bool
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vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID)
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{
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return (rqID >= 2 * hw->num_rx_queues &&
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rqID < 3 * hw->num_rx_queues);
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}
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/*
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* RX/TX function prototypes
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*/
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void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
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void vmxnet3_dev_rx_queue_release(void *rxq);
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void vmxnet3_dev_tx_queue_release(void *txq);
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int vmxnet3_v4_rss_configure(struct rte_eth_dev *dev);
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int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
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int vmxnet3_rss_configure(struct rte_eth_dev *dev);
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uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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#define VMXNET3_SEGS_DYNFIELD_NAME "rte_net_vmxnet3_dynfield_segs"
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typedef uint8_t vmxnet3_segs_dynfield_t;
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extern int vmxnet3_segs_dynfield_offset;
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static inline vmxnet3_segs_dynfield_t *
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vmxnet3_segs_dynfield(struct rte_mbuf *mbuf)
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{
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return RTE_MBUF_DYNFIELD(mbuf, \
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vmxnet3_segs_dynfield_offset, vmxnet3_segs_dynfield_t *);
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}
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#endif /* _VMXNET3_ETHDEV_H_ */
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