c3def6a872
This patch enables i40e driver in PowerPC along with its altivec intrinsic support. Signed-off-by: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com> Acked-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
655 lines
20 KiB
C
655 lines
20 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2017 IBM Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <rte_ethdev.h>
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#include <rte_malloc.h>
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#include "base/i40e_prototype.h"
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#include "base/i40e_type.h"
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#include "i40e_ethdev.h"
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#include "i40e_rxtx.h"
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#include "i40e_rxtx_vec_common.h"
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#include <altivec.h>
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#pragma GCC diagnostic ignored "-Wcast-qual"
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static inline void
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i40e_rxq_rearm(struct i40e_rx_queue *rxq)
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{
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int i;
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uint16_t rx_id;
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volatile union i40e_rx_desc *rxdp;
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struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
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struct rte_mbuf *mb0, *mb1;
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vector unsigned long hdr_room = (vector unsigned long){
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RTE_PKTMBUF_HEADROOM,
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RTE_PKTMBUF_HEADROOM};
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vector unsigned long dma_addr0, dma_addr1;
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rxdp = rxq->rx_ring + rxq->rxrearm_start;
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/* Pull 'n' more MBUFs into the software ring */
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if (rte_mempool_get_bulk(rxq->mp,
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(void *)rxep,
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RTE_I40E_RXQ_REARM_THRESH) < 0) {
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if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
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rxq->nb_rx_desc) {
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dma_addr0 = (vector unsigned long){};
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for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
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rxep[i].mbuf = &rxq->fake_mbuf;
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vec_st(dma_addr0, 0,
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(vector unsigned long *)&rxdp[i].read);
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}
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}
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rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
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RTE_I40E_RXQ_REARM_THRESH;
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return;
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}
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/* Initialize the mbufs in vector, process 2 mbufs in one loop */
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for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
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vector unsigned long vaddr0, vaddr1;
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uintptr_t p0, p1;
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mb0 = rxep[0].mbuf;
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mb1 = rxep[1].mbuf;
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/* Flush mbuf with pkt template.
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* Data to be rearmed is 6 bytes long.
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* Though, RX will overwrite ol_flags that are coming next
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* anyway. So overwrite whole 8 bytes with one load:
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* 6 bytes of rearm_data plus first 2 bytes of ol_flags.
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*/
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p0 = (uintptr_t)&mb0->rearm_data;
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*(uint64_t *)p0 = rxq->mbuf_initializer;
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p1 = (uintptr_t)&mb1->rearm_data;
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*(uint64_t *)p1 = rxq->mbuf_initializer;
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/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
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vaddr0 = vec_ld(0, (vector unsigned long *)&mb0->buf_addr);
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vaddr1 = vec_ld(0, (vector unsigned long *)&mb1->buf_addr);
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/* convert pa to dma_addr hdr/data */
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dma_addr0 = vec_mergel(vaddr0, vaddr0);
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dma_addr1 = vec_mergel(vaddr1, vaddr1);
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/* add headroom to pa values */
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dma_addr0 = vec_add(dma_addr0, hdr_room);
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dma_addr1 = vec_add(dma_addr1, hdr_room);
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/* flush desc with pa dma_addr */
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vec_st(dma_addr0, 0, (vector unsigned long *)&rxdp++->read);
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vec_st(dma_addr1, 0, (vector unsigned long *)&rxdp++->read);
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}
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rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
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if (rxq->rxrearm_start >= rxq->nb_rx_desc)
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rxq->rxrearm_start = 0;
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rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
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rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
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(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
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/* Update the tail pointer on the NIC */
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I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
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}
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/* Handling the offload flags (olflags) field takes computation
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* time when receiving packets. Therefore we provide a flag to disable
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* the processing of the olflags field when they are not needed. This
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* gives improved performance, at the cost of losing the offload info
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* in the received packet
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*/
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#ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
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static inline void
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desc_to_olflags_v(vector unsigned long descs[4], struct rte_mbuf **rx_pkts)
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{
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vector unsigned int vlan0, vlan1, rss, l3_l4e;
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/* mask everything except RSS, flow director and VLAN flags
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* bit2 is for VLAN tag, bit11 for flow director indication
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* bit13:12 for RSS indication.
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*/
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const vector unsigned int rss_vlan_msk = (vector unsigned int){
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(int32_t)0x1c03804, (int32_t)0x1c03804,
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(int32_t)0x1c03804, (int32_t)0x1c03804};
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/* map rss and vlan type to rss hash and vlan flag */
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const vector unsigned char vlan_flags = (vector unsigned char){
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0, 0, 0, 0,
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PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0};
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const vector unsigned char rss_flags = (vector unsigned char){
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0, PKT_RX_FDIR, 0, 0,
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0, 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH | PKT_RX_FDIR,
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0, 0, 0, 0,
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0, 0, 0, 0};
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const vector unsigned char l3_l4e_flags = (vector unsigned char){
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0,
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PKT_RX_IP_CKSUM_BAD,
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PKT_RX_L4_CKSUM_BAD,
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PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
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PKT_RX_EIP_CKSUM_BAD,
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PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
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PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
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PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
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| PKT_RX_IP_CKSUM_BAD,
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0, 0, 0, 0, 0, 0, 0, 0};
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vlan0 = (vector unsigned int)vec_mergel(descs[0], descs[1]);
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vlan1 = (vector unsigned int)vec_mergel(descs[2], descs[3]);
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vlan0 = (vector unsigned int)vec_mergeh(vlan0, vlan1);
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vlan1 = vec_and(vlan0, rss_vlan_msk);
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vlan0 = (vector unsigned int)vec_perm(vlan_flags,
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(vector unsigned char){},
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*(vector unsigned char *)&vlan1);
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rss = vec_sr(vlan1, (vector unsigned int){11, 11, 11, 11});
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rss = (vector unsigned int)vec_perm(rss_flags, (vector unsigned char){},
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*(vector unsigned char *)&rss);
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l3_l4e = vec_sr(vlan1, (vector unsigned int){22, 22, 22, 22});
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l3_l4e = (vector unsigned int)vec_perm(l3_l4e_flags,
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(vector unsigned char){},
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*(vector unsigned char *)&l3_l4e);
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vlan0 = vec_or(vlan0, rss);
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vlan0 = vec_or(vlan0, l3_l4e);
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rx_pkts[0]->ol_flags = (uint64_t)vlan0[2];
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rx_pkts[1]->ol_flags = (uint64_t)vlan0[3];
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rx_pkts[2]->ol_flags = (uint64_t)vlan0[0];
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rx_pkts[3]->ol_flags = (uint64_t)vlan0[1];
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}
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#else
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#define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
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#endif
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#define PKTLEN_SHIFT 10
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static inline void
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desc_to_ptype_v(vector unsigned long descs[4], struct rte_mbuf **rx_pkts)
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{
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vector unsigned long ptype0 = vec_mergel(descs[0], descs[1]);
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vector unsigned long ptype1 = vec_mergel(descs[2], descs[3]);
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ptype0 = vec_sr(ptype0, (vector unsigned long){30, 30});
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ptype1 = vec_sr(ptype1, (vector unsigned long){30, 30});
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rx_pkts[0]->packet_type = i40e_rxd_pkt_type_mapping(
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(*(vector unsigned char *)&ptype0)[0]);
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rx_pkts[1]->packet_type = i40e_rxd_pkt_type_mapping(
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(*(vector unsigned char *)&ptype0)[8]);
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rx_pkts[2]->packet_type = i40e_rxd_pkt_type_mapping(
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(*(vector unsigned char *)&ptype1)[0]);
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rx_pkts[3]->packet_type = i40e_rxd_pkt_type_mapping(
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(*(vector unsigned char *)&ptype1)[8]);
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}
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/* Notice:
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* - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
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* - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
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* numbers of DD bits
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*/
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static inline uint16_t
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_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts, uint8_t *split_packet)
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{
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volatile union i40e_rx_desc *rxdp;
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struct i40e_rx_entry *sw_ring;
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uint16_t nb_pkts_recd;
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int pos;
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uint64_t var;
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vector unsigned char shuf_msk;
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vector unsigned short crc_adjust = (vector unsigned short){
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0, 0, /* ignore pkt_type field */
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rxq->crc_len, /* sub crc on pkt_len */
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0, /* ignore high-16bits of pkt_len */
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rxq->crc_len, /* sub crc on data_len */
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0, 0, 0 /* ignore non-length fields */
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};
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vector unsigned long dd_check, eop_check;
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/* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
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nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
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/* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
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nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
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/* Just the act of getting into the function from the application is
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* going to cost about 7 cycles
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*/
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rxdp = rxq->rx_ring + rxq->rx_tail;
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rte_prefetch0(rxdp);
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/* See if we need to rearm the RX queue - gives the prefetch a bit
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* of time to act
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*/
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if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
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i40e_rxq_rearm(rxq);
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/* Before we start moving massive data around, check to see if
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* there is actually a packet available
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*/
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if (!(rxdp->wb.qword1.status_error_len &
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rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
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return 0;
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/* 4 packets DD mask */
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dd_check = (vector unsigned long){0x0000000100000001ULL,
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0x0000000100000001ULL};
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/* 4 packets EOP mask */
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eop_check = (vector unsigned long){0x0000000200000002ULL,
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0x0000000200000002ULL};
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/* mask to shuffle from desc. to mbuf */
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shuf_msk = (vector unsigned char){
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0xFF, 0xFF, /* pkt_type set as unknown */
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0xFF, 0xFF, /* pkt_type set as unknown */
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14, 15, /* octet 15~14, low 16 bits pkt_len */
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0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
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14, 15, /* octet 15~14, 16 bits data_len */
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2, 3, /* octet 2~3, low 16 bits vlan_macip */
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4, 5, 6, 7 /* octet 4~7, 32bits rss */
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};
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/* Cache is empty -> need to scan the buffer rings, but first move
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* the next 'n' mbufs into the cache
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*/
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sw_ring = &rxq->sw_ring[rxq->rx_tail];
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/* A. load 4 packet in one loop
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* [A*. mask out 4 unused dirty field in desc]
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* B. copy 4 mbuf point from swring to rx_pkts
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* C. calc the number of DD bits among the 4 packets
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* [C*. extract the end-of-packet bit, if requested]
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* D. fill info. from desc to mbuf
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*/
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for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
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pos += RTE_I40E_DESCS_PER_LOOP,
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rxdp += RTE_I40E_DESCS_PER_LOOP) {
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vector unsigned long descs[RTE_I40E_DESCS_PER_LOOP];
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vector unsigned char pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
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vector unsigned short staterr, sterr_tmp1, sterr_tmp2;
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vector unsigned long mbp1, mbp2; /* two mbuf pointer
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* in one XMM reg.
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*/
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/* B.1 load 1 mbuf point */
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mbp1 = *(vector unsigned long *)&sw_ring[pos];
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/* Read desc statuses backwards to avoid race condition */
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/* A.1 load 4 pkts desc */
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descs[3] = *(vector unsigned long *)(rxdp + 3);
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rte_compiler_barrier();
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/* B.2 copy 2 mbuf point into rx_pkts */
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*(vector unsigned long *)&rx_pkts[pos] = mbp1;
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/* B.1 load 1 mbuf point */
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mbp2 = *(vector unsigned long *)&sw_ring[pos + 2];
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descs[2] = *(vector unsigned long *)(rxdp + 2);
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rte_compiler_barrier();
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/* B.1 load 2 mbuf point */
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descs[1] = *(vector unsigned long *)(rxdp + 1);
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rte_compiler_barrier();
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descs[0] = *(vector unsigned long *)(rxdp);
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/* B.2 copy 2 mbuf point into rx_pkts */
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*(vector unsigned long *)&rx_pkts[pos + 2] = mbp2;
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if (split_packet) {
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rte_mbuf_prefetch_part2(rx_pkts[pos]);
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rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
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rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
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rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
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}
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/* avoid compiler reorder optimization */
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rte_compiler_barrier();
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/* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
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const vector unsigned int len3 = vec_sl(
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vec_ld(0, (vector unsigned int *)&descs[3]),
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(vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
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const vector unsigned int len2 = vec_sl(
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vec_ld(0, (vector unsigned int *)&descs[2]),
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(vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
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/* merge the now-aligned packet length fields back in */
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descs[3] = (vector unsigned long)len3;
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descs[2] = (vector unsigned long)len2;
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/* D.1 pkt 3,4 convert format from desc to pktmbuf */
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pkt_mb4 = vec_perm((vector unsigned char)descs[3],
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(vector unsigned char){}, shuf_msk);
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pkt_mb3 = vec_perm((vector unsigned char)descs[2],
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(vector unsigned char){}, shuf_msk);
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/* C.1 4=>2 filter staterr info only */
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sterr_tmp2 = vec_mergel((vector unsigned short)descs[3],
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(vector unsigned short)descs[2]);
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/* C.1 4=>2 filter staterr info only */
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sterr_tmp1 = vec_mergel((vector unsigned short)descs[1],
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(vector unsigned short)descs[0]);
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/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
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pkt_mb4 = (vector unsigned char)vec_sub(
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(vector unsigned short)pkt_mb4, crc_adjust);
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pkt_mb3 = (vector unsigned char)vec_sub(
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(vector unsigned short)pkt_mb3, crc_adjust);
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/* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
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const vector unsigned int len1 = vec_sl(
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vec_ld(0, (vector unsigned int *)&descs[1]),
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(vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
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const vector unsigned int len0 = vec_sl(
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vec_ld(0, (vector unsigned int *)&descs[0]),
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(vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
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/* merge the now-aligned packet length fields back in */
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descs[1] = (vector unsigned long)len1;
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descs[0] = (vector unsigned long)len0;
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/* D.1 pkt 1,2 convert format from desc to pktmbuf */
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pkt_mb2 = vec_perm((vector unsigned char)descs[1],
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(vector unsigned char){}, shuf_msk);
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pkt_mb1 = vec_perm((vector unsigned char)descs[0],
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(vector unsigned char){}, shuf_msk);
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/* C.2 get 4 pkts staterr value */
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staterr = (vector unsigned short)vec_mergeh(
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sterr_tmp1, sterr_tmp2);
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/* D.3 copy final 3,4 data to rx_pkts */
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vec_st(pkt_mb4, 0,
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(vector unsigned char *)&rx_pkts[pos + 3]
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->rx_descriptor_fields1
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);
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vec_st(pkt_mb3, 0,
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(vector unsigned char *)&rx_pkts[pos + 2]
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->rx_descriptor_fields1
|
|
);
|
|
|
|
/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
|
|
pkt_mb2 = (vector unsigned char)vec_sub(
|
|
(vector unsigned short)pkt_mb2, crc_adjust);
|
|
pkt_mb1 = (vector unsigned char)vec_sub(
|
|
(vector unsigned short)pkt_mb1, crc_adjust);
|
|
|
|
/* C* extract and record EOP bit */
|
|
if (split_packet) {
|
|
vector unsigned char eop_shuf_mask =
|
|
(vector unsigned char){
|
|
0xFF, 0xFF, 0xFF, 0xFF,
|
|
0xFF, 0xFF, 0xFF, 0xFF,
|
|
0xFF, 0xFF, 0xFF, 0xFF,
|
|
0x04, 0x0C, 0x00, 0x08
|
|
};
|
|
|
|
/* and with mask to extract bits, flipping 1-0 */
|
|
vector unsigned char eop_bits = vec_and(
|
|
(vector unsigned char)vec_nor(staterr, staterr),
|
|
(vector unsigned char)eop_check);
|
|
/* the staterr values are not in order, as the count
|
|
* count of dd bits doesn't care. However, for end of
|
|
* packet tracking, we do care, so shuffle. This also
|
|
* compresses the 32-bit values to 8-bit
|
|
*/
|
|
eop_bits = vec_perm(eop_bits, (vector unsigned char){},
|
|
eop_shuf_mask);
|
|
/* store the resulting 32-bit value */
|
|
*split_packet = (vec_ld(0,
|
|
(vector unsigned int *)&eop_bits))[0];
|
|
split_packet += RTE_I40E_DESCS_PER_LOOP;
|
|
|
|
/* zero-out next pointers */
|
|
rx_pkts[pos]->next = NULL;
|
|
rx_pkts[pos + 1]->next = NULL;
|
|
rx_pkts[pos + 2]->next = NULL;
|
|
rx_pkts[pos + 3]->next = NULL;
|
|
}
|
|
|
|
/* C.3 calc available number of desc */
|
|
staterr = vec_and(staterr, (vector unsigned short)dd_check);
|
|
|
|
/* D.3 copy final 1,2 data to rx_pkts */
|
|
vec_st(pkt_mb2, 0,
|
|
(vector unsigned char *)&rx_pkts[pos + 1]
|
|
->rx_descriptor_fields1
|
|
);
|
|
vec_st(pkt_mb1, 0,
|
|
(vector unsigned char *)&rx_pkts[pos]->rx_descriptor_fields1
|
|
);
|
|
desc_to_ptype_v(descs, &rx_pkts[pos]);
|
|
desc_to_olflags_v(descs, &rx_pkts[pos]);
|
|
|
|
/* C.4 calc avaialbe number of desc */
|
|
var = __builtin_popcountll((vec_ld(0,
|
|
(vector unsigned long *)&staterr)[0]));
|
|
nb_pkts_recd += var;
|
|
if (likely(var != RTE_I40E_DESCS_PER_LOOP))
|
|
break;
|
|
}
|
|
|
|
/* Update our internal tail pointer */
|
|
rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
|
|
rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
|
|
rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
|
|
|
|
return nb_pkts_recd;
|
|
}
|
|
|
|
/* Notice:
|
|
* - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
|
|
* - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
|
|
* numbers of DD bits
|
|
*/
|
|
uint16_t
|
|
i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
|
|
}
|
|
|
|
/* vPMD receive routine that reassembles scattered packets
|
|
* Notice:
|
|
* - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
|
|
* - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
|
|
* numbers of DD bits
|
|
*/
|
|
uint16_t
|
|
i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
struct i40e_rx_queue *rxq = rx_queue;
|
|
uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
|
|
|
|
/* get some new buffers */
|
|
uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
|
|
split_flags);
|
|
if (nb_bufs == 0)
|
|
return 0;
|
|
|
|
/* happy day case, full burst + no packets to be joined */
|
|
const uint64_t *split_fl64 = (uint64_t *)split_flags;
|
|
|
|
if (rxq->pkt_first_seg == NULL &&
|
|
split_fl64[0] == 0 && split_fl64[1] == 0 &&
|
|
split_fl64[2] == 0 && split_fl64[3] == 0)
|
|
return nb_bufs;
|
|
|
|
/* reassemble any packets that need reassembly*/
|
|
unsigned int i = 0;
|
|
|
|
if (!rxq->pkt_first_seg) {
|
|
/* find the first split flag, and only reassemble then*/
|
|
while (i < nb_bufs && !split_flags[i])
|
|
i++;
|
|
if (i == nb_bufs)
|
|
return nb_bufs;
|
|
}
|
|
return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
|
|
&split_flags[i]);
|
|
}
|
|
|
|
static inline void
|
|
vtx1(volatile struct i40e_tx_desc *txdp,
|
|
struct rte_mbuf *pkt, uint64_t flags)
|
|
{
|
|
uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
|
|
((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
|
|
((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
|
|
|
|
vector unsigned long descriptor = (vector unsigned long){
|
|
pkt->buf_physaddr + pkt->data_off, high_qw};
|
|
*(vector unsigned long *)txdp = descriptor;
|
|
}
|
|
|
|
static inline void
|
|
vtx(volatile struct i40e_tx_desc *txdp,
|
|
struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
|
|
vtx1(txdp, *pkt, flags);
|
|
}
|
|
|
|
uint16_t
|
|
i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
|
|
volatile struct i40e_tx_desc *txdp;
|
|
struct i40e_tx_entry *txep;
|
|
uint16_t n, nb_commit, tx_id;
|
|
uint64_t flags = I40E_TD_CMD;
|
|
uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
|
|
int i;
|
|
|
|
/* cross rx_thresh boundary is not allowed */
|
|
nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
|
|
|
|
if (txq->nb_tx_free < txq->tx_free_thresh)
|
|
i40e_tx_free_bufs(txq);
|
|
|
|
nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
|
|
nb_commit = nb_pkts;
|
|
if (unlikely(nb_pkts == 0))
|
|
return 0;
|
|
|
|
tx_id = txq->tx_tail;
|
|
txdp = &txq->tx_ring[tx_id];
|
|
txep = &txq->sw_ring[tx_id];
|
|
|
|
txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
|
|
|
|
n = (uint16_t)(txq->nb_tx_desc - tx_id);
|
|
if (nb_commit >= n) {
|
|
tx_backlog_entry(txep, tx_pkts, n);
|
|
|
|
for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
|
|
vtx1(txdp, *tx_pkts, flags);
|
|
|
|
vtx1(txdp, *tx_pkts++, rs);
|
|
|
|
nb_commit = (uint16_t)(nb_commit - n);
|
|
|
|
tx_id = 0;
|
|
txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
|
|
|
|
/* avoid reach the end of ring */
|
|
txdp = &txq->tx_ring[tx_id];
|
|
txep = &txq->sw_ring[tx_id];
|
|
}
|
|
|
|
tx_backlog_entry(txep, tx_pkts, nb_commit);
|
|
|
|
vtx(txdp, tx_pkts, nb_commit, flags);
|
|
|
|
tx_id = (uint16_t)(tx_id + nb_commit);
|
|
if (tx_id > txq->tx_next_rs) {
|
|
txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
|
|
rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
|
|
I40E_TXD_QW1_CMD_SHIFT);
|
|
txq->tx_next_rs =
|
|
(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
|
|
}
|
|
|
|
txq->tx_tail = tx_id;
|
|
|
|
I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
|
|
|
|
return nb_pkts;
|
|
}
|
|
|
|
void __attribute__((cold))
|
|
i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
|
|
{
|
|
_i40e_rx_queue_release_mbufs_vec(rxq);
|
|
}
|
|
|
|
int __attribute__((cold))
|
|
i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
|
|
{
|
|
return i40e_rxq_vec_setup_default(rxq);
|
|
}
|
|
|
|
int __attribute__((cold))
|
|
i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused * txq)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int __attribute__((cold))
|
|
i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
|
|
{
|
|
return i40e_rx_vec_dev_conf_condition_check_default(dev);
|
|
}
|