f947fd7718
For HMAC algorithms (MD5-HMAC, SHAx-HMAC), the supported key sizes are not a fixed value, but a range between 1 and the block size. Fixes: 623326dded3a ("crypto/dpaa2_sec: introduce poll mode driver") Cc: stable@dpdk.org Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
415 lines
10 KiB
C
415 lines
10 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2016 NXP.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Freescale Semiconductor, Inc nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTE_DPAA2_SEC_PMD_PRIVATE_H_
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#define _RTE_DPAA2_SEC_PMD_PRIVATE_H_
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#define CRYPTODEV_NAME_DPAA2_SEC_PMD crypto_dpaa2_sec
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/**< NXP DPAA2 - SEC PMD device name */
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#define MAX_QUEUES 64
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#define MAX_DESC_SIZE 64
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/** private data structure for each DPAA2_SEC device */
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struct dpaa2_sec_dev_private {
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void *mc_portal; /**< MC Portal for configuring this device */
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void *hw; /**< Hardware handle for this device.Used by NADK framework */
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struct rte_mempool *fle_pool; /* per device memory pool for FLE */
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int32_t hw_id; /**< An unique ID of this device instance */
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int32_t vfio_fd; /**< File descriptor received via VFIO */
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uint16_t token; /**< Token required by DPxxx objects */
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unsigned int max_nb_queue_pairs;
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/**< Max number of queue pairs supported by device */
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unsigned int max_nb_sessions;
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/**< Max number of sessions supported by device */
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};
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struct dpaa2_sec_qp {
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struct dpaa2_queue rx_vq;
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struct dpaa2_queue tx_vq;
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};
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enum shr_desc_type {
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DESC_UPDATE,
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DESC_FINAL,
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DESC_INITFINAL,
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};
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#define DIR_ENC 1
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#define DIR_DEC 0
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/* SEC Flow Context Descriptor */
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struct sec_flow_context {
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/* word 0 */
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uint16_t word0_sdid; /* 11-0 SDID */
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uint16_t word0_res; /* 31-12 reserved */
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/* word 1 */
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uint8_t word1_sdl; /* 5-0 SDL */
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/* 7-6 reserved */
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uint8_t word1_bits_15_8; /* 11-8 CRID */
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/* 14-12 reserved */
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/* 15 CRJD */
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uint8_t word1_bits23_16; /* 16 EWS */
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/* 17 DAC */
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/* 18,19,20 ? */
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/* 23-21 reserved */
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uint8_t word1_bits31_24; /* 24 RSC */
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/* 25 RBMT */
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/* 31-26 reserved */
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/* word 2 RFLC[31-0] */
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uint32_t word2_rflc_31_0;
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/* word 3 RFLC[63-32] */
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uint32_t word3_rflc_63_32;
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/* word 4 */
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uint16_t word4_iicid; /* 15-0 IICID */
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uint16_t word4_oicid; /* 31-16 OICID */
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/* word 5 */
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uint32_t word5_ofqid:24; /* 23-0 OFQID */
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uint32_t word5_31_24:8;
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/* 24 OSC */
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/* 25 OBMT */
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/* 29-26 reserved */
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/* 31-30 ICR */
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/* word 6 */
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uint32_t word6_oflc_31_0;
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/* word 7 */
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uint32_t word7_oflc_63_32;
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/* Word 8-15 storage profiles */
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uint16_t dl; /**< DataLength(correction) */
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uint16_t reserved; /**< reserved */
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uint16_t dhr; /**< DataHeadRoom(correction) */
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uint16_t mode_bits; /**< mode bits */
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uint16_t bpv0; /**< buffer pool0 valid */
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uint16_t bpid0; /**< Bypass Memory Translation */
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uint16_t bpv1; /**< buffer pool1 valid */
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uint16_t bpid1; /**< Bypass Memory Translation */
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uint64_t word_12_15[2]; /**< word 12-15 are reserved */
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};
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struct sec_flc_desc {
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struct sec_flow_context flc;
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uint32_t desc[MAX_DESC_SIZE];
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};
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struct ctxt_priv {
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struct rte_mempool *fle_pool; /* per device memory pool for FLE */
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struct sec_flc_desc flc_desc[0];
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};
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enum dpaa2_sec_op_type {
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DPAA2_SEC_NONE, /*!< No Cipher operations*/
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DPAA2_SEC_CIPHER,/*!< CIPHER operations */
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DPAA2_SEC_AUTH, /*!< Authentication Operations */
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DPAA2_SEC_AEAD, /*!< AEAD (AES-GCM/CCM) type operations */
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DPAA2_SEC_CIPHER_HASH, /*!< Authenticated Encryption with
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* associated data
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*/
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DPAA2_SEC_HASH_CIPHER, /*!< Encryption with Authenticated
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* associated data
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*/
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DPAA2_SEC_IPSEC, /*!< IPSEC protocol operations*/
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DPAA2_SEC_PDCP, /*!< PDCP protocol operations*/
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DPAA2_SEC_PKC, /*!< Public Key Cryptographic Operations */
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DPAA2_SEC_MAX
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};
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struct dpaa2_sec_aead_ctxt {
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uint16_t auth_only_len; /*!< Length of data for Auth only */
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uint8_t auth_cipher_text; /**< Authenticate/cipher ordering */
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};
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typedef struct dpaa2_sec_session_entry {
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void *ctxt;
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uint8_t ctxt_type;
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uint8_t dir; /*!< Operation Direction */
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enum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/
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enum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/
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union {
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struct {
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uint8_t *data; /**< pointer to key data */
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size_t length; /**< key length in bytes */
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} aead_key;
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struct {
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struct {
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uint8_t *data; /**< pointer to key data */
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size_t length; /**< key length in bytes */
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} cipher_key;
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struct {
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uint8_t *data; /**< pointer to key data */
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size_t length; /**< key length in bytes */
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} auth_key;
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};
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};
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struct {
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uint16_t length; /**< IV length in bytes */
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uint16_t offset; /**< IV offset in bytes */
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} iv;
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uint16_t digest_length;
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uint8_t status;
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union {
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struct dpaa2_sec_aead_ctxt aead_ctxt;
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} ext_params;
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} dpaa2_sec_session;
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static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {
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{ /* MD5 HMAC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
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{.auth = {
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.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
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.block_size = 64,
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.key_size = {
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.min = 1,
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.max = 64,
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.increment = 1
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},
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.digest_size = {
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.min = 16,
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.max = 16,
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.increment = 0
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},
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.iv_size = { 0 }
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}, }
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}, }
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},
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{ /* SHA1 HMAC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
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{.auth = {
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.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
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.block_size = 64,
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.key_size = {
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.min = 1,
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.max = 64,
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.increment = 1
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},
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.digest_size = {
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.min = 20,
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.max = 20,
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.increment = 0
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},
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.iv_size = { 0 }
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}, }
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}, }
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},
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{ /* SHA224 HMAC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
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{.auth = {
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.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
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.block_size = 64,
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.key_size = {
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.min = 1,
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.max = 64,
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.increment = 1
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},
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.digest_size = {
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.min = 28,
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.max = 28,
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.increment = 0
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},
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.iv_size = { 0 }
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}, }
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}, }
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},
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{ /* SHA256 HMAC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
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{.auth = {
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.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
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.block_size = 64,
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.key_size = {
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.min = 1,
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.max = 64,
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.increment = 1
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},
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.digest_size = {
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.min = 32,
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.max = 32,
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.increment = 0
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},
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.iv_size = { 0 }
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}, }
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}, }
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},
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{ /* SHA384 HMAC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
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{.auth = {
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.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
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.block_size = 128,
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.key_size = {
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.min = 1,
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.max = 128,
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.increment = 1
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},
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.digest_size = {
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.min = 48,
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.max = 48,
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.increment = 0
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},
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.iv_size = { 0 }
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}, }
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}, }
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},
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{ /* SHA512 HMAC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
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{.auth = {
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.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
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.block_size = 128,
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.key_size = {
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.min = 1,
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.max = 128,
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.increment = 1
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},
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.digest_size = {
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.min = 64,
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.max = 64,
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.increment = 0
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},
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.iv_size = { 0 }
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}, }
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}, }
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},
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{ /* AES GCM */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
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{.aead = {
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.algo = RTE_CRYPTO_AEAD_AES_GCM,
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.block_size = 16,
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.key_size = {
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.min = 16,
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.max = 32,
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.increment = 8
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},
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.digest_size = {
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.min = 8,
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.max = 16,
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.increment = 4
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},
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.aad_size = {
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.min = 0,
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.max = 240,
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.increment = 1
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},
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.iv_size = {
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.min = 12,
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.max = 12,
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.increment = 0
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},
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}, }
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}, }
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},
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{ /* AES CBC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
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{.cipher = {
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.algo = RTE_CRYPTO_CIPHER_AES_CBC,
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.block_size = 16,
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.key_size = {
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.min = 16,
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.max = 32,
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.increment = 8
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},
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.iv_size = {
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.min = 16,
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.max = 16,
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.increment = 0
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}
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}, }
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}, }
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},
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{ /* AES CTR */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
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{.cipher = {
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.algo = RTE_CRYPTO_CIPHER_AES_CTR,
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.block_size = 16,
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.key_size = {
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.min = 16,
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.max = 32,
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.increment = 8
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},
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.iv_size = {
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.min = 16,
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.max = 16,
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.increment = 0
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},
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}, }
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}, }
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},
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{ /* 3DES CBC */
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.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
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{.sym = {
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.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
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{.cipher = {
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.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
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.block_size = 8,
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.key_size = {
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.min = 16,
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.max = 24,
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.increment = 8
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},
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.iv_size = {
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.min = 8,
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.max = 8,
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.increment = 0
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}
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}, }
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}, }
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},
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RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
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};
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#endif /* _RTE_DPAA2_SEC_PMD_PRIVATE_H_ */
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