0dc02cca8b
The first and last memory pool elements are usually cache-aligned but not page-aligned, particularly when using huge pages. Hardware performance can be improved significantly by registering memory regions starting and ending on page boundaries. Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com> |
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Makefile | ||
mlx4.c | ||
mlx4.h | ||
rte_pmd_mlx4_version.map |