aee2733fe3
Clarify Intel copyright and update the date to 2020.
Fixes: 8cb7c57d9b ("net/igc: support device initialization")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
297 lines
12 KiB
C
297 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2020 Intel Corporation
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*/
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#ifndef _IGC_ICH8LAN_H_
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#define _IGC_ICH8LAN_H_
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#define ICH_FLASH_GFPREG 0x0000
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#define ICH_FLASH_HSFSTS 0x0004
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#define ICH_FLASH_HSFCTL 0x0006
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#define ICH_FLASH_FADDR 0x0008
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#define ICH_FLASH_FDATA0 0x0010
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/* Requires up to 10 seconds when MNG might be accessing part. */
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#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
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#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
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#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
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#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
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#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
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#define ICH_CYCLE_READ 0
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#define ICH_CYCLE_WRITE 2
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#define ICH_CYCLE_ERASE 3
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#define FLASH_GFPREG_BASE_MASK 0x1FFF
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#define FLASH_SECTOR_ADDR_SHIFT 12
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#define ICH_FLASH_SEG_SIZE_256 256
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#define ICH_FLASH_SEG_SIZE_4K 4096
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#define ICH_FLASH_SEG_SIZE_8K 8192
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#define ICH_FLASH_SEG_SIZE_64K 65536
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#define IGC_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
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/* FW established a valid mode */
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#define IGC_ICH_FWSM_FW_VALID 0x00008000
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#define IGC_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
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#define IGC_ICH_FWSM_PCIM2PCI_COUNT 2000
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#define IGC_ICH_MNG_IAMT_MODE 0x2
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#define IGC_FWSM_WLOCK_MAC_MASK 0x0380
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#define IGC_FWSM_WLOCK_MAC_SHIFT 7
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#define IGC_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
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/* Shared Receive Address Registers */
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#define IGC_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
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#define IGC_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
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#define IGC_H2ME 0x05B50 /* Host to ME */
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#define IGC_H2ME_ULP 0x00000800 /* ULP Indication Bit */
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#define IGC_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
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#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_OFF1_OFF2 << 8) | \
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(ID_LED_OFF1_ON2 << 4) | \
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(ID_LED_DEF1_DEF2))
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#define IGC_ICH_NVM_SIG_WORD 0x13
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#define IGC_ICH_NVM_SIG_MASK 0xC000
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#define IGC_ICH_NVM_VALID_SIG_MASK 0xC0
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#define IGC_ICH_NVM_SIG_VALUE 0x80
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#define IGC_ICH8_LAN_INIT_TIMEOUT 1500
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/* FEXT register bit definition */
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#define IGC_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
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#define IGC_FEXTNVM_SW_CONFIG 1
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#define IGC_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
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#define IGC_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
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#define IGC_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
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#define IGC_FEXTNVM4_BEACON_DURATION_MASK 0x7
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#define IGC_FEXTNVM4_BEACON_DURATION_8USEC 0x7
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#define IGC_FEXTNVM4_BEACON_DURATION_16USEC 0x3
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#define IGC_FEXTNVM6_REQ_PLL_CLK 0x00000100
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#define IGC_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
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#define IGC_FEXTNVM6_K1_OFF_ENABLE 0x80000000
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/* bit for disabling packet buffer read */
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#define IGC_FEXTNVM7_DISABLE_PB_READ 0x00040000
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#define IGC_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
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#define IGC_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
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#define IGC_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
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#define IGC_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
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#define IGC_FEXTNVM11_DISABLE_PB_READ 0x00000200
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#define IGC_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
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/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
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#define IGC_RXDCTL_THRESH_UNIT_DESC 0x01000000
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#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/
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#define IGC_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
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#define IGC_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
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#define IGC_TARC0_CB_MULTIQ_3_REQ 0x30000000
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#define IGC_TARC0_CB_MULTIQ_2_REQ 0x20000000
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#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
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#define IGC_ICH_RAR_ENTRIES 7
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#define IGC_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
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#define IGC_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
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#define PHY_PAGE_SHIFT 5
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#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
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((reg) & MAX_PHY_REG_ADDRESS))
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#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
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#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
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#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
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#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
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/* PHY Wakeup Registers and defines */
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#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
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#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
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#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
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#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
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#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
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#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
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#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
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#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
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#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
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#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
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#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
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#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
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#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
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#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
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#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
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#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
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#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
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#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
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#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
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#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
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#define HV_STATS_PAGE 778
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/* Half-duplex collision counts */
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#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
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#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
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#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
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#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
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#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
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#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
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#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
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#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
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#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
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#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
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#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
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#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
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#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
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#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
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#define IGC_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
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#define IGC_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
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#define IGC_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
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#define K1_ENTRY_LATENCY 0
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#define K1_MIN_TIME 1
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/* SMBus Control Phy Register */
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#define CV_SMB_CTRL PHY_REG(769, 23)
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#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
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/* I218 Ultra Low Power Configuration 1 Register */
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#define I218_ULP_CONFIG1 PHY_REG(779, 16)
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#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
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#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
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#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
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#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
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#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
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#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
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/* enable ULP even if when phy powered down via lanphypc */
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#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400
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/* disable clear of sticky ULP on PERST */
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#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800
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#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
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/* SMBus Address Phy Register */
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#define HV_SMB_ADDR PHY_REG(768, 26)
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#define HV_SMB_ADDR_MASK 0x007F
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#define HV_SMB_ADDR_PEC_EN 0x0200
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#define HV_SMB_ADDR_VALID 0x0080
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#define HV_SMB_ADDR_FREQ_MASK 0x1100
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#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
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#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
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/* Strapping Option Register - RO */
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#define IGC_STRAP 0x0000C
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#define IGC_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
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#define IGC_STRAP_SMBUS_ADDRESS_SHIFT 17
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#define IGC_STRAP_SMT_FREQ_MASK 0x00003000
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#define IGC_STRAP_SMT_FREQ_SHIFT 12
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/* OEM Bits Phy Register */
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#define HV_OEM_BITS PHY_REG(768, 25)
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#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
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#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
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#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
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/* KMRN Mode Control */
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#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
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#define HV_KMRN_MDIO_SLOW 0x0400
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/* KMRN FIFO Control and Status */
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#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
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#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
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#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
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/* PHY Power Management Control */
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#define HV_PM_CTRL PHY_REG(770, 17)
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#define HV_PM_CTRL_K1_CLK_REQ 0x200
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#define HV_PM_CTRL_K1_ENABLE 0x4000
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#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
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#define I217_PLL_CLOCK_GATE_MASK 0x07FF
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#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
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/* Inband Control */
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#define I217_INBAND_CTRL PHY_REG(770, 18)
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#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
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#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8
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/* Low Power Idle GPIO Control */
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#define I217_LPI_GPIO_CTRL PHY_REG(772, 18)
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#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800
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/* PHY Low Power Idle Control */
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#define I82579_LPI_CTRL PHY_REG(772, 20)
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#define I82579_LPI_CTRL_100_ENABLE 0x2000
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#define I82579_LPI_CTRL_1000_ENABLE 0x4000
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#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
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/* 82579 DFT Control */
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#define I82579_DFT_CTRL PHY_REG(769, 20)
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#define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */
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/* Extended Management Interface (EMI) Registers */
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#define I82579_EMI_ADDR 0x10
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#define I82579_EMI_DATA 0x11
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#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
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#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
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#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
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#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
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#define I82579_RX_CONFIG 0x3412 /* Receive configuration */
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#define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
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#define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
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#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
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#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
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#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
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#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
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#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
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#define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */
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#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
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#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
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#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
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#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
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#define I217_RX_CONFIG 0xB20C /* Receive configuration */
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#define IGC_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
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#define IGC_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
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/* Intel Rapid Start Technology Support */
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#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
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#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
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#define I217_CGFREG PHY_REG(772, 29)
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#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
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#define I217_MEMPWR PHY_REG(772, 26)
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#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
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/* Receive Address Initial CRC Calculation */
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#define IGC_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
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#define IGC_PCI_VENDOR_ID_REGISTER 0x00
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#define IGC_PCI_REVISION_ID_REG 0x08
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void igc_set_kmrn_lock_loss_workaround_ich8lan(struct igc_hw *hw,
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bool state);
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void igc_igp3_phy_powerdown_workaround_ich8lan(struct igc_hw *hw);
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void igc_gig_downshift_workaround_ich8lan(struct igc_hw *hw);
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void igc_suspend_workarounds_ich8lan(struct igc_hw *hw);
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u32 igc_resume_workarounds_pchlan(struct igc_hw *hw);
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s32 igc_configure_k1_ich8lan(struct igc_hw *hw, bool k1_enable);
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s32 igc_configure_k0s_lpt(struct igc_hw *hw, u8 entry_latency, u8 min_time);
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void igc_copy_rx_addrs_to_phy_ich8lan(struct igc_hw *hw);
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s32 igc_lv_jumbo_workaround_ich8lan(struct igc_hw *hw, bool enable);
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s32 igc_read_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 *data);
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s32 igc_write_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 data);
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s32 igc_set_eee_pchlan(struct igc_hw *hw);
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s32 igc_enable_ulp_lpt_lp(struct igc_hw *hw, bool to_sx);
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s32 igc_disable_ulp_lpt_lp(struct igc_hw *hw, bool force);
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#endif /* _IGC_ICH8LAN_H_ */
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void igc_demote_ltr(struct igc_hw *hw, bool demote, bool link);
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