aee2733fe3
Clarify Intel copyright and update the date to 2020.
Fixes: 8cb7c57d9b ("net/igc: support device initialization")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019-2020 Intel Corporation
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*/
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#ifndef _IGC_OSDEP_H_
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#define _IGC_OSDEP_H_
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#include <stdint.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <stdbool.h>
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_log.h>
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#include <rte_debug.h>
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#include <rte_byteorder.h>
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#include <rte_io.h>
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#include "../igc_logs.h"
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#define DELAY(x) rte_delay_us(x)
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#define usec_delay(x) DELAY(x)
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#define usec_delay_irq(x) DELAY(x)
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#define msec_delay(x) DELAY(1000 * (x))
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#define msec_delay_irq(x) DELAY(1000 * (x))
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#define DEBUGFUNC(F) DEBUGOUT(F "\n")
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#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
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#define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
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#define UNREFERENCED_PARAMETER(_p) (void)(_p)
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#define UNREFERENCED_1PARAMETER(_p) (void)(_p)
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#define UNREFERENCED_2PARAMETER(_p, _q) \
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do { \
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(void)(_p); \
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(void)(_q); \
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} while (0)
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#define UNREFERENCED_3PARAMETER(_p, _q, _r) \
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do { \
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(void)(_p); \
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(void)(_q); \
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(void)(_r); \
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} while (0)
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#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) \
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do { \
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(void)(_p); \
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(void)(_q); \
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(void)(_r); \
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(void)(_s); \
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} while (0)
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#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
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/* Mutex used in the shared code */
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#define IGC_MUTEX uintptr_t
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#define IGC_MUTEX_INIT(mutex) (*(mutex) = 0)
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#define IGC_MUTEX_LOCK(mutex) (*(mutex) = 1)
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#define IGC_MUTEX_UNLOCK(mutex) (*(mutex) = 0)
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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#define __le16 u16
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#define __le32 u32
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#define __le64 u64
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#define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS)
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#define IGC_PCI_REG(reg) rte_read32(reg)
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#define IGC_PCI_REG16(reg) rte_read16(reg)
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#define IGC_PCI_REG_WRITE(reg, value) \
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rte_write32((rte_cpu_to_le_32(value)), reg)
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#define IGC_PCI_REG_WRITE_RELAXED(reg, value) \
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rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
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#define IGC_PCI_REG_WRITE16(reg, value) \
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rte_write16((rte_cpu_to_le_16(value)), reg)
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#define IGC_PCI_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
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#define IGC_PCI_REG_ARRAY_ADDR(hw, reg, index) \
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IGC_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
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#define IGC_PCI_REG_FLASH_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
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static inline uint32_t igc_read_addr(volatile void *addr)
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{
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return rte_le_to_cpu_32(IGC_PCI_REG(addr));
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}
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static inline uint16_t igc_read_addr16(volatile void *addr)
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{
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return rte_le_to_cpu_16(IGC_PCI_REG16(addr));
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}
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/* Register READ/WRITE macros */
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#define IGC_READ_REG(hw, reg) \
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igc_read_addr(IGC_PCI_REG_ADDR((hw), (reg)))
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#define IGC_READ_REG_LE_VALUE(hw, reg) \
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rte_read32(IGC_PCI_REG_ADDR((hw), (reg)))
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#define IGC_WRITE_REG(hw, reg, value) \
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IGC_PCI_REG_WRITE(IGC_PCI_REG_ADDR((hw), (reg)), (value))
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#define IGC_WRITE_REG_LE_VALUE(hw, reg, value) \
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rte_write32(value, IGC_PCI_REG_ADDR((hw), (reg)))
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#define IGC_READ_REG_ARRAY(hw, reg, index) \
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IGC_PCI_REG(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
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#define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \
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IGC_PCI_REG_WRITE(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), \
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(value))
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#define IGC_READ_REG_ARRAY_DWORD IGC_READ_REG_ARRAY
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#define IGC_WRITE_REG_ARRAY_DWORD IGC_WRITE_REG_ARRAY
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/*
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* To be able to do IO write, we need to map IO BAR
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* (bar 2/4 depending on device).
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* Right now mapping multiple BARs is not supported by DPDK.
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* Fortunatelly we need it only for legacy hw support.
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*/
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#define IGC_WRITE_REG_IO(hw, reg, value) \
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IGC_WRITE_REG(hw, reg, value)
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/*
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* Tested on I217/I218 chipset.
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*/
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#define IGC_READ_FLASH_REG(hw, reg) \
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igc_read_addr(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))
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#define IGC_READ_FLASH_REG16(hw, reg) \
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igc_read_addr16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))
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#define IGC_WRITE_FLASH_REG(hw, reg, value) \
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IGC_PCI_REG_WRITE(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
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#define IGC_WRITE_FLASH_REG16(hw, reg, value) \
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IGC_PCI_REG_WRITE16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
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#endif /* _IGC_OSDEP_H_ */
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