63a97e588b
The device private pointer (dev_private) is of type void * therefore no cast is necessary in C. Cc: stable@dpdk.org Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
832 lines
25 KiB
C
832 lines
25 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Chelsio Communications.
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* All rights reserved.
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*/
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/* This file should not be included directly. Include common.h instead. */
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#ifndef __T4_ADAPTER_H__
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#define __T4_ADAPTER_H__
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#include <rte_bus_pci.h>
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#include <rte_mbuf.h>
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#include <rte_io.h>
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#include <rte_rwlock.h>
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#include <rte_ethdev.h>
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#include "../cxgbe_compat.h"
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#include "../cxgbe_ofld.h"
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#include "t4_regs_values.h"
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enum {
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MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
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MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
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};
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struct adapter;
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struct sge_rspq;
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enum {
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PORT_RSS_DONE = (1 << 0),
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};
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struct port_info {
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struct adapter *adapter; /* adapter that this port belongs to */
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struct rte_eth_dev *eth_dev; /* associated rte eth device */
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struct port_stats stats_base; /* port statistics base */
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struct link_config link_cfg; /* link configuration info */
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unsigned long flags; /* port related flags */
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short int xact_addr_filt; /* index of exact MAC address filter */
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u16 viid; /* associated virtual interface id */
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s8 mdio_addr; /* address of the PHY */
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u8 port_type; /* firmware port type */
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u8 mod_type; /* firmware module type */
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u8 port_id; /* physical port ID */
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u8 pidx; /* port index for this PF */
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u8 tx_chan; /* associated channel */
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u8 n_rx_qsets; /* # of rx qsets */
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u8 n_tx_qsets; /* # of tx qsets */
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u8 first_qset; /* index of first qset */
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u16 *rss; /* rss table */
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u8 rss_mode; /* rss mode */
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u16 rss_size; /* size of VI's RSS table slice */
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u64 rss_hf; /* RSS Hash Function */
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};
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/* Enable or disable autonegotiation. If this is set to enable,
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* the forced link modes above are completely ignored.
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*/
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#define AUTONEG_DISABLE 0x00
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#define AUTONEG_ENABLE 0x01
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enum { /* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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USING_MSI = (1 << 1),
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USING_MSIX = (1 << 2),
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FW_QUEUE_BOUND = (1 << 3),
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FW_OK = (1 << 4),
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CFG_QUEUES = (1 << 5),
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MASTER_PF = (1 << 6),
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};
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struct rx_sw_desc { /* SW state per Rx descriptor */
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void *buf; /* struct page or mbuf */
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dma_addr_t dma_addr;
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};
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struct sge_fl { /* SGE free-buffer queue state */
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/* RO fields */
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struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
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dma_addr_t addr; /* bus address of HW ring start */
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__be64 *desc; /* address of HW Rx descriptor ring */
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void __iomem *bar2_addr; /* address of BAR2 Queue registers */
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unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
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unsigned int cntxt_id; /* SGE relative QID for the free list */
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unsigned int size; /* capacity of free list */
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unsigned int avail; /* # of available Rx buffers */
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unsigned int pend_cred; /* new buffers since last FL DB ring */
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unsigned int cidx; /* consumer index */
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unsigned int pidx; /* producer index */
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unsigned long alloc_failed; /* # of times buffer allocation failed */
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unsigned long low; /* # of times momentarily starving */
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};
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#define MAX_MBUF_FRAGS (16384 / 512 + 2)
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/* A packet gather list */
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struct pkt_gl {
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union {
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struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
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} /* UNNAMED */;
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void *va; /* virtual address of first byte */
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unsigned int nfrags; /* # of fragments */
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unsigned int tot_len; /* total length of fragments */
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bool usembufs; /* use mbufs for fragments */
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};
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typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
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const struct pkt_gl *gl);
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struct sge_rspq { /* state for an SGE response queue */
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struct adapter *adapter; /* adapter that this queue belongs to */
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struct rte_eth_dev *eth_dev; /* associated rte eth device */
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struct rte_mempool *mb_pool; /* associated mempool */
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dma_addr_t phys_addr; /* physical address of the ring */
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__be64 *desc; /* address of HW response ring */
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const __be64 *cur_desc; /* current descriptor in queue */
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void __iomem *bar2_addr; /* address of BAR2 Queue registers */
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unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
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struct sge_qstat *stat;
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unsigned int cidx; /* consumer index */
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unsigned int gts_idx; /* last gts write sent */
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unsigned int iqe_len; /* entry size */
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unsigned int size; /* capacity of response queue */
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int offset; /* offset into current Rx buffer */
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u8 gen; /* current generation bit */
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u8 intr_params; /* interrupt holdoff parameters */
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u8 next_intr_params; /* holdoff params for next interrupt */
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u8 pktcnt_idx; /* interrupt packet threshold */
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u8 port_id; /* associated port-id */
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u8 idx; /* queue index within its group */
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u16 cntxt_id; /* SGE relative QID for the response Q */
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u16 abs_id; /* absolute SGE id for the response q */
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rspq_handler_t handler; /* associated handler for this response q */
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};
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struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
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u64 pkts; /* # of ethernet packets */
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u64 rx_bytes; /* # of ethernet bytes */
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u64 rx_cso; /* # of Rx checksum offloads */
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u64 vlan_ex; /* # of Rx VLAN extractions */
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u64 rx_drops; /* # of packets dropped due to no mem */
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};
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struct sge_eth_rxq { /* a SW Ethernet Rx queue */
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struct sge_rspq rspq;
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struct sge_fl fl;
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struct sge_eth_rx_stats stats;
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bool usembufs; /* one ingress packet per mbuf FL buffer */
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} __rte_cache_aligned;
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/*
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* Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
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* packet (if one sgl is present) and type 1 needs 32 bytes. This means
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* that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
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* 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
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* to be able to free those mbufs when we get completions back from the FW.
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* Allocating the maximum number of pointers in every tx desc is a waste
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* of memory resources so we only store 2 pointers per tx desc which should
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* be enough since a tx desc can only fit 2 packets in the best case
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* scenario where a packet needs 32 bytes.
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*/
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#define ETH_COALESCE_PKT_NUM 15
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#define ETH_COALESCE_VF_PKT_NUM 7
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#define ETH_COALESCE_PKT_PER_DESC 2
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struct tx_eth_coal_desc {
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struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
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struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
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int idx;
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};
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struct tx_desc {
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__be64 flit[8];
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};
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struct tx_sw_desc { /* SW state per Tx descriptor */
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struct rte_mbuf *mbuf;
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struct ulptx_sgl *sgl;
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struct tx_eth_coal_desc coalesce;
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};
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enum {
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EQ_STOPPED = (1 << 0),
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};
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struct eth_coalesce {
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unsigned char *ptr;
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unsigned char type;
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unsigned int idx;
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unsigned int len;
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unsigned int flits;
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unsigned int max;
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__u8 ethmacdst[ETHER_ADDR_LEN];
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__u8 ethmacsrc[ETHER_ADDR_LEN];
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__be16 ethtype;
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__be16 vlantci;
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};
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struct sge_txq {
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struct tx_desc *desc; /* address of HW Tx descriptor ring */
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struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
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struct sge_qstat *stat; /* queue status entry */
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struct eth_coalesce coalesce; /* coalesce info */
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uint64_t phys_addr; /* physical address of the ring */
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void __iomem *bar2_addr; /* address of BAR2 Queue registers */
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unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
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unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
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unsigned int in_use; /* # of in-use Tx descriptors */
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unsigned int size; /* # of descriptors */
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unsigned int cidx; /* SW consumer index */
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unsigned int pidx; /* producer index */
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unsigned int dbidx; /* last idx when db ring was done */
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unsigned int equeidx; /* last sent credit request */
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unsigned int last_pidx; /* last pidx recorded by tx monitor */
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unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
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unsigned int abs_id;
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int db_disabled; /* doorbell state */
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unsigned short db_pidx; /* doorbell producer index */
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unsigned short db_pidx_inc; /* doorbell producer increment */
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};
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struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
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u64 pkts; /* # of ethernet packets */
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u64 tx_bytes; /* # of ethernet bytes */
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u64 tso; /* # of TSO requests */
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u64 tx_cso; /* # of Tx checksum offloads */
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u64 vlan_ins; /* # of Tx VLAN insertions */
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u64 mapping_err; /* # of I/O MMU packet mapping errors */
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u64 coal_wr; /* # of coalesced wr */
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u64 coal_pkts; /* # of coalesced packets */
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};
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struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
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struct sge_txq q;
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struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
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struct rte_eth_dev_data *data;
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struct sge_eth_tx_stats stats; /* queue statistics */
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rte_spinlock_t txq_lock;
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unsigned int flags; /* flags for state of the queue */
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} __rte_cache_aligned;
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struct sge_ctrl_txq { /* State for an SGE control Tx queue */
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struct sge_txq q; /* txq */
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struct adapter *adapter; /* adapter associated with this queue */
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rte_spinlock_t ctrlq_lock; /* control queue lock */
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u8 full; /* the Tx ring is full */
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u64 txp; /* number of transmits */
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struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
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} __rte_cache_aligned;
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struct sge {
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struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
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struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
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struct sge_rspq fw_evtq __rte_cache_aligned;
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struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
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u16 max_ethqsets; /* # of available Ethernet queue sets */
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u32 stat_len; /* length of status page at ring end */
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u32 pktshift; /* padding between CPL & packet data */
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/* response queue interrupt parameters */
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u16 timer_val[SGE_NTIMERS];
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u8 counter_val[SGE_NCOUNTERS];
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u32 fl_align; /* response queue message alignment */
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u32 fl_pg_order; /* large page allocation size */
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u32 fl_starve_thres; /* Free List starvation threshold */
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};
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#define T4_OS_NEEDS_MBOX_LOCKING 1
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/*
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* OS Lock/List primitives for those interfaces in the Common Code which
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* need this.
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*/
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struct mbox_entry {
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TAILQ_ENTRY(mbox_entry) next;
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};
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TAILQ_HEAD(mbox_list, mbox_entry);
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struct adapter {
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struct rte_pci_device *pdev; /* associated rte pci device */
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struct rte_eth_dev *eth_dev; /* first port's rte eth device */
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struct adapter_params params; /* adapter parameters */
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struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
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struct sge sge; /* associated SGE */
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/* support for single-threading access to adapter mailbox registers */
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struct mbox_list mbox_list;
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rte_spinlock_t mbox_lock;
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u8 *regs; /* pointer to registers region */
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u8 *bar2; /* pointer to bar2 region */
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unsigned long flags; /* adapter flags */
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unsigned int mbox; /* associated mailbox */
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unsigned int pf; /* associated physical function id */
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unsigned int vpd_busy;
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unsigned int vpd_flag;
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int use_unpacked_mode; /* unpacked rx mode state */
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rte_spinlock_t win0_lock;
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unsigned int clipt_start; /* CLIP table start */
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unsigned int clipt_end; /* CLIP table end */
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unsigned int l2t_start; /* Layer 2 table start */
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unsigned int l2t_end; /* Layer 2 table end */
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struct clip_tbl *clipt; /* CLIP table */
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struct l2t_data *l2t; /* Layer 2 table */
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struct mpstcam_table *mpstcam;
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struct tid_info tids; /* Info used to access TID related tables */
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};
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/**
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* t4_os_rwlock_init - initialize rwlock
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* @lock: the rwlock
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*/
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static inline void t4_os_rwlock_init(rte_rwlock_t *lock)
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{
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rte_rwlock_init(lock);
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}
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/**
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* t4_os_write_lock - get a write lock
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* @lock: the rwlock
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*/
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static inline void t4_os_write_lock(rte_rwlock_t *lock)
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{
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rte_rwlock_write_lock(lock);
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}
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/**
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* t4_os_write_unlock - unlock a write lock
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* @lock: the rwlock
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*/
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static inline void t4_os_write_unlock(rte_rwlock_t *lock)
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{
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rte_rwlock_write_unlock(lock);
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}
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/**
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* ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
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* @dev: the rte_eth_dev
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*
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* Return the struct port_info associated with a rte_eth_dev
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*/
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static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
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{
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return dev->data->dev_private;
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}
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/**
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* adap2pinfo - return the port_info of a port
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* @adap: the adapter
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* @idx: the port index
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*
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* Return the port_info structure for the port of the given index.
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*/
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static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
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{
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return adap->port[idx];
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}
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/**
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* ethdev2adap - return the adapter structure associated with a rte_eth_dev
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* @dev: the rte_eth_dev
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*
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* Return the struct adapter associated with a rte_eth_dev
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*/
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static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
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{
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return ethdev2pinfo(dev)->adapter;
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}
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#define CXGBE_PCI_REG(reg) rte_read32(reg)
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static inline uint64_t cxgbe_read_addr64(volatile void *addr)
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{
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uint64_t val = CXGBE_PCI_REG(addr);
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uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
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val2 = (uint64_t)(val2 << 32);
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val += val2;
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return val;
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}
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static inline uint32_t cxgbe_read_addr(volatile void *addr)
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{
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return CXGBE_PCI_REG(addr);
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}
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#define CXGBE_PCI_REG_ADDR(adap, reg) \
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((volatile uint32_t *)((char *)(adap)->regs + (reg)))
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#define CXGBE_READ_REG(adap, reg) \
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cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
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#define CXGBE_READ_REG64(adap, reg) \
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cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
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#define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
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#define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
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rte_write32_relaxed((value), (reg))
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#define CXGBE_WRITE_REG(adap, reg, value) \
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CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
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#define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
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CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
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static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
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{
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CXGBE_PCI_REG_WRITE(addr, val);
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CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
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return val;
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}
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#define CXGBE_WRITE_REG64(adap, reg, value) \
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cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
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/**
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* t4_read_reg - read a HW register
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* @adapter: the adapter
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* @reg_addr: the register address
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*
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* Returns the 32-bit value of the given HW register.
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*/
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static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
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{
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u32 val = CXGBE_READ_REG(adapter, reg_addr);
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CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
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val);
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return val;
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}
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/**
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* t4_write_reg - write a HW register with barrier
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* @adapter: the adapter
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* @reg_addr: the register address
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* @val: the value to write
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*
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* Write a 32-bit value into the given HW register.
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*/
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static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
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{
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CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
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val);
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CXGBE_WRITE_REG(adapter, reg_addr, val);
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}
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/**
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* t4_write_reg_relaxed - write a HW register with no barrier
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* @adapter: the adapter
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* @reg_addr: the register address
|
|
* @val: the value to write
|
|
*
|
|
* Write a 32-bit value into the given HW register.
|
|
*/
|
|
static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
|
|
u32 val)
|
|
{
|
|
CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
|
|
val);
|
|
CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
|
|
}
|
|
|
|
/**
|
|
* t4_read_reg64 - read a 64-bit HW register
|
|
* @adapter: the adapter
|
|
* @reg_addr: the register address
|
|
*
|
|
* Returns the 64-bit value of the given HW register.
|
|
*/
|
|
static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
|
|
{
|
|
u64 val = CXGBE_READ_REG64(adapter, reg_addr);
|
|
|
|
CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
|
|
reg_addr, (unsigned long long)val);
|
|
return val;
|
|
}
|
|
|
|
/**
|
|
* t4_write_reg64 - write a 64-bit HW register
|
|
* @adapter: the adapter
|
|
* @reg_addr: the register address
|
|
* @val: the value to write
|
|
*
|
|
* Write a 64-bit value into the given HW register.
|
|
*/
|
|
static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
|
|
u64 val)
|
|
{
|
|
CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
|
|
(unsigned long long)val);
|
|
|
|
CXGBE_WRITE_REG64(adapter, reg_addr, val);
|
|
}
|
|
|
|
#define PCI_STATUS 0x06 /* 16 bits */
|
|
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
|
|
#define PCI_CAPABILITY_LIST 0x34
|
|
/* Offset of first capability list entry */
|
|
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
|
|
#define PCI_CAP_LIST_ID 0 /* Capability ID */
|
|
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
|
|
#define PCI_EXP_DEVCTL 0x0008 /* Device control */
|
|
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
|
|
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
|
|
#define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
|
|
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
|
|
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
|
|
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
|
|
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
|
|
|
|
/**
|
|
* t4_os_pci_write_cfg4 - 32-bit write to PCI config space
|
|
* @adapter: the adapter
|
|
* @addr: the register address
|
|
* @val: the value to write
|
|
*
|
|
* Write a 32-bit value into the given register in PCI config space.
|
|
*/
|
|
static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
|
|
off_t val)
|
|
{
|
|
u32 val32 = val;
|
|
|
|
if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
|
|
addr) < 0)
|
|
dev_err(adapter, "Can't write to PCI config space\n");
|
|
}
|
|
|
|
/**
|
|
* t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
|
|
* @adapter: the adapter
|
|
* @addr: the register address
|
|
* @val: where to store the value read
|
|
*
|
|
* Read a 32-bit value from the given register in PCI config space.
|
|
*/
|
|
static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
|
|
u32 *val)
|
|
{
|
|
if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
|
|
addr) < 0)
|
|
dev_err(adapter, "Can't read from PCI config space\n");
|
|
}
|
|
|
|
/**
|
|
* t4_os_pci_write_cfg2 - 16-bit write to PCI config space
|
|
* @adapter: the adapter
|
|
* @addr: the register address
|
|
* @val: the value to write
|
|
*
|
|
* Write a 16-bit value into the given register in PCI config space.
|
|
*/
|
|
static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
|
|
off_t val)
|
|
{
|
|
u16 val16 = val;
|
|
|
|
if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
|
|
addr) < 0)
|
|
dev_err(adapter, "Can't write to PCI config space\n");
|
|
}
|
|
|
|
/**
|
|
* t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
|
|
* @adapter: the adapter
|
|
* @addr: the register address
|
|
* @val: where to store the value read
|
|
*
|
|
* Read a 16-bit value from the given register in PCI config space.
|
|
*/
|
|
static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
|
|
u16 *val)
|
|
{
|
|
if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
|
|
addr) < 0)
|
|
dev_err(adapter, "Can't read from PCI config space\n");
|
|
}
|
|
|
|
/**
|
|
* t4_os_pci_read_cfg - read a 8-bit value from PCI config space
|
|
* @adapter: the adapter
|
|
* @addr: the register address
|
|
* @val: where to store the value read
|
|
*
|
|
* Read a 8-bit value from the given register in PCI config space.
|
|
*/
|
|
static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
|
|
u8 *val)
|
|
{
|
|
if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
|
|
addr) < 0)
|
|
dev_err(adapter, "Can't read from PCI config space\n");
|
|
}
|
|
|
|
/**
|
|
* t4_os_find_pci_capability - lookup a capability in the PCI capability list
|
|
* @adapter: the adapter
|
|
* @cap: the capability
|
|
*
|
|
* Return the address of the given capability within the PCI capability list.
|
|
*/
|
|
static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
|
|
{
|
|
u16 status;
|
|
int ttl = 48;
|
|
u8 pos = 0;
|
|
u8 id = 0;
|
|
|
|
t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
|
|
if (!(status & PCI_STATUS_CAP_LIST)) {
|
|
dev_err(adapter, "PCIe capability reading failed\n");
|
|
return -1;
|
|
}
|
|
|
|
t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
|
|
while (ttl-- && pos >= 0x40) {
|
|
pos &= ~3;
|
|
t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
|
|
|
|
if (id == 0xff)
|
|
break;
|
|
|
|
if (id == cap)
|
|
return (int)pos;
|
|
|
|
t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* t4_os_set_hw_addr - store a port's MAC address in SW
|
|
* @adapter: the adapter
|
|
* @port_idx: the port index
|
|
* @hw_addr: the Ethernet address
|
|
*
|
|
* Store the Ethernet address of the given port in SW. Called by the
|
|
* common code when it retrieves a port's Ethernet address from EEPROM.
|
|
*/
|
|
static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
|
|
u8 hw_addr[])
|
|
{
|
|
struct port_info *pi = adap2pinfo(adapter, port_idx);
|
|
|
|
rte_ether_addr_copy((struct rte_ether_addr *)hw_addr,
|
|
&pi->eth_dev->data->mac_addrs[0]);
|
|
}
|
|
|
|
/**
|
|
* t4_os_lock_init - initialize spinlock
|
|
* @lock: the spinlock
|
|
*/
|
|
static inline void t4_os_lock_init(rte_spinlock_t *lock)
|
|
{
|
|
rte_spinlock_init(lock);
|
|
}
|
|
|
|
/**
|
|
* t4_os_lock - spin until lock is acquired
|
|
* @lock: the spinlock
|
|
*/
|
|
static inline void t4_os_lock(rte_spinlock_t *lock)
|
|
{
|
|
rte_spinlock_lock(lock);
|
|
}
|
|
|
|
/**
|
|
* t4_os_unlock - unlock a spinlock
|
|
* @lock: the spinlock
|
|
*/
|
|
static inline void t4_os_unlock(rte_spinlock_t *lock)
|
|
{
|
|
rte_spinlock_unlock(lock);
|
|
}
|
|
|
|
/**
|
|
* t4_os_trylock - try to get a lock
|
|
* @lock: the spinlock
|
|
*/
|
|
static inline int t4_os_trylock(rte_spinlock_t *lock)
|
|
{
|
|
return rte_spinlock_trylock(lock);
|
|
}
|
|
|
|
/**
|
|
* t4_os_init_list_head - initialize
|
|
* @head: head of list to initialize [to empty]
|
|
*/
|
|
static inline void t4_os_init_list_head(struct mbox_list *head)
|
|
{
|
|
TAILQ_INIT(head);
|
|
}
|
|
|
|
static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
|
|
{
|
|
return TAILQ_FIRST(head);
|
|
}
|
|
|
|
/**
|
|
* t4_os_atomic_add_tail - Enqueue list element atomically onto list
|
|
* @new: the entry to be addded to the queue
|
|
* @head: current head of the linked list
|
|
* @lock: lock to use to guarantee atomicity
|
|
*/
|
|
static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
|
|
struct mbox_list *head,
|
|
rte_spinlock_t *lock)
|
|
{
|
|
t4_os_lock(lock);
|
|
TAILQ_INSERT_TAIL(head, entry, next);
|
|
t4_os_unlock(lock);
|
|
}
|
|
|
|
/**
|
|
* t4_os_atomic_list_del - Dequeue list element atomically from list
|
|
* @entry: the entry to be remove/dequeued from the list.
|
|
* @lock: the spinlock
|
|
*/
|
|
static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
|
|
struct mbox_list *head,
|
|
rte_spinlock_t *lock)
|
|
{
|
|
t4_os_lock(lock);
|
|
TAILQ_REMOVE(head, entry, next);
|
|
t4_os_unlock(lock);
|
|
}
|
|
|
|
/**
|
|
* t4_init_completion - initialize completion
|
|
* @c: the completion context
|
|
*/
|
|
static inline void t4_init_completion(struct t4_completion *c)
|
|
{
|
|
c->done = 0;
|
|
t4_os_lock_init(&c->lock);
|
|
}
|
|
|
|
/**
|
|
* t4_complete - set completion as done
|
|
* @c: the completion context
|
|
*/
|
|
static inline void t4_complete(struct t4_completion *c)
|
|
{
|
|
t4_os_lock(&c->lock);
|
|
c->done = 1;
|
|
t4_os_unlock(&c->lock);
|
|
}
|
|
|
|
/**
|
|
* cxgbe_port_viid - get the VI id of a port
|
|
* @dev: the device for the port
|
|
*
|
|
* Return the VI id of the given port.
|
|
*/
|
|
static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev)
|
|
{
|
|
return ethdev2pinfo(dev)->viid;
|
|
}
|
|
|
|
void *t4_alloc_mem(size_t size);
|
|
void t4_free_mem(void *addr);
|
|
#define t4_os_alloc(_size) t4_alloc_mem((_size))
|
|
#define t4_os_free(_ptr) t4_free_mem((_ptr))
|
|
|
|
void t4_os_portmod_changed(const struct adapter *adap, int port_id);
|
|
void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
|
|
|
|
void reclaim_completed_tx(struct sge_txq *q);
|
|
void t4_free_sge_resources(struct adapter *adap);
|
|
void t4_sge_tx_monitor_start(struct adapter *adap);
|
|
void t4_sge_tx_monitor_stop(struct adapter *adap);
|
|
int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
|
|
uint16_t nb_pkts);
|
|
int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
|
|
int t4_sge_init(struct adapter *adap);
|
|
int t4vf_sge_init(struct adapter *adap);
|
|
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
|
|
struct rte_eth_dev *eth_dev, uint16_t queue_id,
|
|
unsigned int iqid, int socket_id);
|
|
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
|
|
struct rte_eth_dev *eth_dev, uint16_t queue_id,
|
|
unsigned int iqid, int socket_id);
|
|
int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
|
|
struct rte_eth_dev *eth_dev, int intr_idx,
|
|
struct sge_fl *fl, rspq_handler_t handler,
|
|
int cong, struct rte_mempool *mp, int queue_id,
|
|
int socket_id);
|
|
int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
|
|
int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
|
|
void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
|
|
int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
|
|
int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
|
|
void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
|
|
void t4_sge_eth_clear_queues(struct port_info *pi);
|
|
int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
|
|
unsigned int cnt);
|
|
int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
|
|
unsigned int budget, unsigned int *work_done);
|
|
int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
|
|
int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
|
|
|
|
#endif /* __T4_ADAPTER_H__ */
|