fdd5521006
Fix following build errors reported by Intel C++ compiler in Windows build. C:\> t4_hw.c(5105): warning #147: declaration is incompatible with "int t4_bar2_sge_qregs(struct adapter *, unsigned int, unsigned int, u64={uint64_t={unsigned __int64}} *, unsigned int *)" (declared at line 524 of "..\..\..\..\drivers\net\cxgbe\base\common.h") int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, ^ C:\> cxgbe_filter.c(42): error : expected an expression n_user_filters = mult_frac(adap->tids.nftids, ^ C:\> sge.c(400): error : expression must be a pointer to a complete object type (uint16_t)(RTE_PTR_ALIGN((char *)mbuf->buf_addr + ^ Build Environment: 1. Target OS: Microsoft Windows Server 2016 2. Compiler: Intel C++ Compiler from Intel Parallel Studio XE 2019 [1] 3. Development Tools: 3.1 Microsoft Visual Studio 2017 Professional 3.2 Windows Software Development Kit (SDK) v10.0.17763 3.3 Windows Driver Kit (WDK) v10.0.17763 [1] https://software.intel.com/en-us/parallel-studio-xe Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
550 lines
20 KiB
C
550 lines
20 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Chelsio Communications.
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* All rights reserved.
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*/
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#ifndef __CHELSIO_COMMON_H
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#define __CHELSIO_COMMON_H
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#include "../cxgbe_compat.h"
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#include "t4_hw.h"
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#include "t4vf_hw.h"
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#include "t4_chip_type.h"
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#include "t4fw_interface.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
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#define T4_MEMORY_WRITE 0
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#define T4_MEMORY_READ 1
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enum {
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MAX_NPORTS = 4, /* max # of ports */
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};
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enum {
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T5_REGMAP_SIZE = (332 * 1024),
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};
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enum {
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MEMWIN0_APERTURE = 2048,
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MEMWIN0_BASE = 0x1b800,
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};
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enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
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enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
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enum cc_pause {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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enum cc_fec {
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FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
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FEC_RS = 1 << 1, /* Reed-Solomon */
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FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
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};
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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struct port_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_frames; /* all good frames */
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u64 tx_bcast_frames; /* all broadcast frames */
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u64 tx_mcast_frames; /* all multicast frames */
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u64 tx_ucast_frames; /* all unicast frames */
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u64 tx_error_frames; /* all error frames */
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u64 tx_frames_64; /* # of Tx frames in a particular range */
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u64 tx_frames_65_127;
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u64 tx_frames_128_255;
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u64 tx_frames_256_511;
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u64 tx_frames_512_1023;
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u64 tx_frames_1024_1518;
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u64 tx_frames_1519_max;
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u64 tx_drop; /* # of dropped Tx frames */
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u64 tx_pause; /* # of transmitted pause frames */
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u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
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u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
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u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
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u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
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u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
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u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
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u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
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u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
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u64 rx_octets; /* total # of octets in good frames */
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u64 rx_frames; /* all good frames */
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u64 rx_bcast_frames; /* all broadcast frames */
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u64 rx_mcast_frames; /* all multicast frames */
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u64 rx_ucast_frames; /* all unicast frames */
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u64 rx_too_long; /* # of frames exceeding MTU */
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u64 rx_jabber; /* # of jabber frames */
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u64 rx_fcs_err; /* # of received frames with bad FCS */
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u64 rx_len_err; /* # of received frames with length error */
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u64 rx_symbol_err; /* symbol errors */
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u64 rx_runt; /* # of short frames */
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u64 rx_frames_64; /* # of Rx frames in a particular range */
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u64 rx_frames_65_127;
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u64 rx_frames_128_255;
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u64 rx_frames_256_511;
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u64 rx_frames_512_1023;
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u64 rx_frames_1024_1518;
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u64 rx_frames_1519_max;
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u64 rx_pause; /* # of received pause frames */
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u64 rx_ppp0; /* # of received PPP prio 0 frames */
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u64 rx_ppp1; /* # of received PPP prio 1 frames */
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u64 rx_ppp2; /* # of received PPP prio 2 frames */
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u64 rx_ppp3; /* # of received PPP prio 3 frames */
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u64 rx_ppp4; /* # of received PPP prio 4 frames */
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u64 rx_ppp5; /* # of received PPP prio 5 frames */
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u64 rx_ppp6; /* # of received PPP prio 6 frames */
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u64 rx_ppp7; /* # of received PPP prio 7 frames */
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u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
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u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
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u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
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u64 rx_trunc0; /* buffer-group 0 truncated packets */
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u64 rx_trunc1; /* buffer-group 1 truncated packets */
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u64 rx_trunc2; /* buffer-group 2 truncated packets */
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u64 rx_trunc3; /* buffer-group 3 truncated packets */
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};
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struct sge_params {
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u32 hps; /* host page size for our PF/VF */
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u32 eq_qpp; /* egress queues/page for our PF/VF */
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u32 iq_qpp; /* egress queues/page for our PF/VF */
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};
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struct tp_params {
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unsigned int ntxchan; /* # of Tx channels */
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unsigned int tre; /* log2 of core clocks per TP tick */
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unsigned int dack_re; /* DACK timer resolution */
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unsigned int la_mask; /* what events are recorded by TP LA */
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unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
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u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
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u32 ingress_config; /* cached TP_INGRESS_CONFIG */
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/* cached TP_OUT_CONFIG compressed error vector
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* and passing outer header info for encapsulated packets.
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*/
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int rx_pkt_encap;
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/*
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* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
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* subset of the set of fields which may be present in the Compressed
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* Filter Tuple portion of filters and TCP TCB connections. The
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* fields which are present are controlled by the TP_VLAN_PRI_MAP.
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* Since a variable number of fields may or may not be present, their
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* shifted field positions within the Compressed Filter Tuple may
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* vary, or not even be present if the field isn't selected in
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* TP_VLAN_PRI_MAP. Since some of these fields are needed in various
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* places we store their offsets here, or a -1 if the field isn't
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* present.
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*/
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int vlan_shift;
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int vnic_shift;
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int port_shift;
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int protocol_shift;
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int ethertype_shift;
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int macmatch_shift;
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u64 hash_filter_mask;
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};
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struct vpd_params {
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unsigned int cclk;
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};
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struct pci_params {
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uint16_t vendor_id;
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uint16_t device_id;
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uint32_t vpd_cap_addr;
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uint16_t speed;
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uint8_t width;
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};
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/*
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* Firmware device log.
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*/
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struct devlog_params {
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u32 memtype; /* which memory (EDC0, EDC1, MC) */
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u32 start; /* start of log in firmware memory */
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u32 size; /* size of log */
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};
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struct arch_specific_params {
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u8 nchan;
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u16 mps_rplc_size;
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u16 vfcount;
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u32 sge_fl_db;
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u16 mps_tcam_size;
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};
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/*
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* Global Receive Side Scaling (RSS) parameters in host-native format.
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*/
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struct rss_params {
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unsigned int mode; /* RSS mode */
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union {
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struct {
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uint synmapen:1; /* SYN Map Enable */
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uint syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */
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uint syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */
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uint syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */
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uint syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */
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uint ofdmapen:1; /* Offload Map Enable */
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uint tnlmapen:1; /* Tunnel Map Enable */
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uint tnlalllookup:1; /* Tunnel All Lookup */
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uint hashtoeplitz:1; /* use Toeplitz hash */
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} basicvirtual;
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} u;
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};
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/*
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* Maximum resources provisioned for a PCI PF.
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*/
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struct pf_resources {
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unsigned int neq; /* N egress Qs */
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unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
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};
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/*
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* Maximum resources provisioned for a PCI VF.
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*/
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struct vf_resources {
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unsigned int nvi; /* N virtual interfaces */
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unsigned int neq; /* N egress Qs */
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unsigned int nethctrl; /* N egress ETH or CTRL Qs */
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unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
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unsigned int niq; /* N ingress Qs */
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unsigned int tc; /* PCI-E traffic class */
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unsigned int pmask; /* port access rights mask */
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unsigned int nexactf; /* N exact MPS filters */
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unsigned int r_caps; /* read capabilities */
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unsigned int wx_caps; /* write/execute capabilities */
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};
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struct adapter_params {
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struct sge_params sge;
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struct tp_params tp;
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struct vpd_params vpd;
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struct pci_params pci;
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struct devlog_params devlog;
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struct rss_params rss;
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struct pf_resources pfres;
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struct vf_resources vfres;
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enum pcie_memwin drv_memwin;
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unsigned int sf_size; /* serial flash size in bytes */
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unsigned int sf_nsec; /* # of flash sectors */
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unsigned int fw_vers;
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unsigned int bs_vers;
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unsigned int tp_vers;
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unsigned int er_vers;
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unsigned short mtus[NMTUS];
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unsigned short a_wnd[NCCTRL_WIN];
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unsigned short b_wnd[NCCTRL_WIN];
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unsigned int mc_size; /* MC memory size */
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unsigned int cim_la_size;
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unsigned char nports; /* # of ethernet ports */
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unsigned char portvec;
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unsigned char hash_filter;
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enum chip_type chip; /* chip code */
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struct arch_specific_params arch; /* chip specific params */
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bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
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u8 fw_caps_support; /* 32-bit Port Capabilities */
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u8 filter2_wr_support; /* FW support for FILTER2_WR */
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};
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/* Firmware Port Capabilities types.
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*/
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typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
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typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
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enum fw_caps {
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FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
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FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
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FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
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};
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struct link_config {
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fw_port_cap32_t pcaps; /* link capabilities */
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fw_port_cap32_t acaps; /* advertised capabilities */
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u32 requested_speed; /* speed (Mb/s) user has requested */
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u32 speed; /* actual link speed (Mb/s) */
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enum cc_pause requested_fc; /* flow control user has requested */
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enum cc_pause fc; /* actual link flow control */
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enum cc_fec auto_fec; /* Forward Error Correction
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* "automatic" (IEEE 802.3)
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*/
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enum cc_fec requested_fec; /* Forward Error Correction requested */
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enum cc_fec fec; /* Forward Error Correction actual */
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unsigned char autoneg; /* autonegotiating? */
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unsigned char link_ok; /* link up? */
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unsigned char link_down_rc; /* link down reason */
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};
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#include "adapter.h"
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void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
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u32 val);
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int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
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int polarity,
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int attempts, int delay, u32 *valp);
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static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
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int polarity, int attempts, int delay)
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{
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return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
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delay, NULL);
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}
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static inline int is_pf4(struct adapter *adap)
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{
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return adap->pf == 4;
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}
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#define for_each_port(adapter, iter) \
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for (iter = 0; iter < (adapter)->params.nports; ++iter)
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static inline int is_hashfilter(const struct adapter *adap)
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{
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return adap->params.hash_filter;
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}
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void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
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void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
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unsigned int mask, unsigned int val);
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void t4_intr_enable(struct adapter *adapter);
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void t4_intr_disable(struct adapter *adapter);
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int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
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struct link_config *lc);
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void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
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const unsigned short *alpha, const unsigned short *beta);
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int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
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enum dev_master master, enum dev_state *state);
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int t4_fw_bye(struct adapter *adap, unsigned int mbox);
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int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
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int t4vf_fw_reset(struct adapter *adap);
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int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
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int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
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int t4_fl_pkt_align(struct adapter *adap);
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int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2);
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int t4vf_get_vfres(struct adapter *adap);
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int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
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unsigned int cache_line_size,
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enum chip_type chip_compat);
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int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
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unsigned int cache_line_size);
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int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
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int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int nparams, const u32 *params,
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u32 *val);
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int t4vf_query_params(struct adapter *adap, unsigned int nparams,
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const u32 *params, u32 *vals);
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int t4vf_get_dev_params(struct adapter *adap);
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int t4vf_get_vpd_params(struct adapter *adap);
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int t4vf_get_rss_glb_config(struct adapter *adap);
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int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
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const u32 *params, const u32 *vals);
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int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
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unsigned int pf, unsigned int vf,
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unsigned int nparams, const u32 *params,
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const u32 *val, int timeout);
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int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int nparams, const u32 *params,
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const u32 *val);
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int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
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unsigned int port, unsigned int pf, unsigned int vf,
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unsigned int nmac, u8 *mac, unsigned int *rss_size,
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unsigned int portfunc, unsigned int idstype);
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int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
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unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
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unsigned int *rss_size);
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int t4_free_vi(struct adapter *adap, unsigned int mbox,
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unsigned int pf, unsigned int vf,
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unsigned int viid);
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int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
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int mtu, int promisc, int all_multi, int bcast, int vlanex,
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bool sleep_ok);
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int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
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const u8 *addr, const u8 *mask, unsigned int idx,
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u8 lookup_type, u8 port_id, bool sleep_ok);
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int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
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const u8 *addr, const u8 *mask, unsigned int idx,
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u8 lookup_type, u8 port_id, bool sleep_ok);
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int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
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int idx, const u8 *addr, bool persist, bool add_smt);
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int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
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unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
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int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
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bool rx_en, bool tx_en);
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int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
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unsigned int pf, unsigned int vf, unsigned int iqid,
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unsigned int fl0id, unsigned int fl1id);
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int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int iqtype, unsigned int iqid,
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unsigned int fl0id, unsigned int fl1id);
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int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int eqid);
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int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int eqid);
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static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
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{
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return adap->params.vpd.cclk / 1000;
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}
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static inline unsigned int us_to_core_ticks(const struct adapter *adap,
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unsigned int us)
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{
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return (us * adap->params.vpd.cclk) / 1000;
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}
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static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
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unsigned int ticks)
|
|
{
|
|
/* add Core Clock / 2 to round ticks to nearest uS */
|
|
return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
|
|
adapter->params.vpd.cclk);
|
|
}
|
|
|
|
int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl, bool sleep_ok, int timeout);
|
|
int t4_wr_mbox_meat(struct adapter *adap, int mbox,
|
|
const void __attribute__((__may_alias__)) *cmd, int size,
|
|
void *rpl, bool sleep_ok);
|
|
|
|
static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
|
|
const void *cmd, int size, void *rpl,
|
|
int timeout)
|
|
{
|
|
return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
|
|
timeout);
|
|
}
|
|
|
|
int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
|
|
|
|
static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
|
|
}
|
|
|
|
static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
|
|
}
|
|
|
|
int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
|
|
|
|
static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
|
|
}
|
|
|
|
static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
|
|
}
|
|
|
|
|
|
void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
|
|
unsigned int data_reg, u32 *vals, unsigned int nregs,
|
|
unsigned int start_idx);
|
|
void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
|
|
unsigned int data_reg, const u32 *vals,
|
|
unsigned int nregs, unsigned int start_idx);
|
|
|
|
int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
|
|
int t4_get_pfres(struct adapter *adapter);
|
|
int t4_read_flash(struct adapter *adapter, unsigned int addr,
|
|
unsigned int nwords, u32 *data, int byte_oriented);
|
|
int t4_flash_cfg_addr(struct adapter *adapter);
|
|
unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
|
|
unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
|
|
const char *t4_get_port_type_description(enum fw_port_type port_type);
|
|
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
|
|
void t4vf_get_port_stats(struct adapter *adapter, int pidx,
|
|
struct port_stats *p);
|
|
void t4_get_port_stats_offset(struct adapter *adap, int idx,
|
|
struct port_stats *stats,
|
|
struct port_stats *offset);
|
|
void t4_clr_port_stats(struct adapter *adap, int idx);
|
|
void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
|
|
fw_port_cap32_t acaps);
|
|
void t4_reset_link_config(struct adapter *adap, int idx);
|
|
int t4_get_version_info(struct adapter *adapter);
|
|
void t4_dump_version_info(struct adapter *adapter);
|
|
int t4_get_flash_params(struct adapter *adapter);
|
|
int t4_get_chip_type(struct adapter *adap, int ver);
|
|
int t4_prep_adapter(struct adapter *adapter);
|
|
int t4vf_prep_adapter(struct adapter *adapter);
|
|
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
|
|
int t4vf_port_init(struct adapter *adap);
|
|
int t4_init_rss_mode(struct adapter *adap, int mbox);
|
|
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
|
|
int start, int n, const u16 *rspq, unsigned int nrspq);
|
|
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
|
unsigned int flags, unsigned int defq);
|
|
int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
|
u64 *flags, unsigned int *defq);
|
|
void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
|
|
unsigned int start_index, unsigned int rw);
|
|
void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
|
|
void t4_read_rss_key(struct adapter *adap, u32 *key);
|
|
|
|
enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
|
|
int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
|
|
enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
|
|
unsigned int *pbar2_qid);
|
|
|
|
int t4_init_sge_params(struct adapter *adapter);
|
|
int t4_init_tp_params(struct adapter *adap);
|
|
int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
|
|
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
|
|
unsigned int t4_get_regs_len(struct adapter *adap);
|
|
unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
|
|
void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
|
|
int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
|
|
int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
|
|
int t4_seeprom_wp(struct adapter *adapter, int enable);
|
|
int t4_memory_rw_addr(struct adapter *adap, int win,
|
|
u32 addr, u32 len, void *hbuf, int dir);
|
|
int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
|
|
u32 len, void *hbuf, int dir);
|
|
static inline int t4_memory_rw(struct adapter *adap, int win,
|
|
int mtype, u32 maddr, u32 len,
|
|
void *hbuf, int dir)
|
|
{
|
|
return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
|
|
}
|
|
fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
|
|
#endif /* __CHELSIO_COMMON_H */
|